MAGNITUDE COMPARATOR. SN54LS85 Datasheet

SN54LS85 COMPARATOR. Datasheet pdf. Equivalent

SN54LS85 Datasheet
Recommendation SN54LS85 Datasheet
Part SN54LS85
Description 4-BIT MAGNITUDE COMPARATOR
Feature SN54LS85; SN54/74LS85 4-BIT MAGNITUDE COMPARATOR The SN54/ 74LS85 is a 4-Bit Magnitude Camparator which compar.
Manufacture Motorola Inc
Datasheet
Download SN54LS85 Datasheet




Motorola  Inc SN54LS85
4-BIT MAGNITUDE
COMPARATOR
The SN54/ 74LS85 is a 4-Bit Magnitude Camparator which compares two
4-bit words (A, B), each word having four Parallel Inputs (A0 – A3, B0 – B3); A3,
B3 being the most significant inputs. Operation is not restricted to binary
codes, the device will work with any monotonic code. Three Outputs are
provided: “A greater than B” (OA > B), “A less than B” (OA < B), “A equal to B”
(OA = B). Three Expander Inputs, IA > B, IA < B, IA = B, allow cascading without
external gates. For proper compare operation, the Expander Inputs to the
least significant position must be connected as follows: IA < B= IA > B = L, IA = B
= H. For serial (ripple) expansion, the OA > B, OA < B and OA = B Outputs are
connected respectively to the IA > B, IA < B, and IA = B Inputs of the next most
significant comparator, as shown in Figure 1. Refer to Applications section of
data sheet for high speed method of comparing large words.
The Truth Table on the following page describes the operation of the
SN54 / 74LS85 under all possible logic conditions. The upper 11 lines describe
the normal operation under all conditions that will occur in a single device or
in a series expansion scheme. The lower five lines describe the operation
under abnormal conditions on the cascading inputs. These conditions occur
when the parallel expansion technique is used.
Easily Expandable
Binary or BCD Comparison
OA > B, OA < B, and OA = B Outputs Available
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC A3 B2 A2 A1 B1 A0 B0
16 15 14 13 12 11 10 9
1 2 3 4 56 78
B3 IA<B IA=B IA>B OA>B OA=B OA<B GND
NOTE:
The Flatpak version has the
same pinouts (Connection
Diagram) as the Dual In-Line
Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
A0 – A3, B0 – B3
IA = B
IA < B, IA > B
OA > B
OA < B
OA = B
Parallel Inputs
A = B Expander Inputs
A < B, A > B, Expander Inputs
A Greater Than B Output (Note b)
B Greater Than A Output (Note b)
A Equal to B Output (Note b)
1.5 U.L.
1.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
0.75 U.L.
0.75 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS85
4-BIT MAGNITUDE
COMPARATOR
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
10 12 13 15 9 11 14 1
A0 A1 A2 A3 B0 B1 B2 B3
4 IA>B
OA>B 5
2 IA<B
OA<B 7
3 IA=B
OA=B 6
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-84



Motorola  Inc SN54LS85
LOGIC DIAGRAM
A3 (15)
B3 (1)
SN54 / 74LS85
(13)
A2
B2
(14)
A<B
A=B
(2)
(3)
(4)
A>B
(12)
A1
B1 (11)
(5)
OA>B
(6)
OA=B
(7)
OA<B
(10)
A0
B0 (9)
TRUTH TABLE
COMPARING INPUTS
CASCADING
INPUTS
A3,B3
A3>B3
A3<B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A2,B2
X
X
A2>B2
A2<B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A1,B1
X
X
X
X
A1>B1
A1<B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A0,B0
X
X
X
X
X
X
A0>B0
A0<B0
A0=B0
A0=B0
A0=B0
A0=B0
A0=B0
IA>B
X
X
X
X
X
X
X
X
H
L
X
H
L
IA<B
X
X
X
X
X
X
X
X
L
H
X
H
L
IA=B
X
X
X
X
X
X
X
X
L
L
H
L
L
OUTPUTS
OA>B
H
L
H
L
H
L
H
L
H
L
L
L
H
OA<B
L
H
L
H
L
H
L
H
L
H
L
L
H
OA=B
L
L
L
L
L
L
L
L
L
L
H
L
L
H = HIGH Level
L = LOW Level
X = IMMATERIAL
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
FAST AND LS TTL DATA
5-85



Motorola  Inc SN54LS85
SN54 / 74LS85
A0 A1 A2 A3 B0 B1 B2 B3
A0 A1 A2 A3 B0 B1 B2 B3
L IA > B
OA > B
L IA < B SN54/74LS85 OA < B
H IA = B
OA = B
A0 A1 A2 A3 B0 B1 B2 B3
IA > B
OA > B
IA < B SN54/74LS85 OA < B
IA = B
OA = B
A>B
A<B
A=B
L = LOW LEVEL
H = HIGH LEVEL
Figure 1. Comparing Two n-Bit Words
APPLICATIONS
Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the technique
shown in Figure 1, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expanded
to any number of bits, see Table 1.
Table 1
WORD LENGTH NUMBER OF PKGS.
1 – 4 Bits
5 – 24 Bits
25 – 120 Bits
1
2–6
8 – 31
(LSB)
A0 A1 A2 A3 B0 B1 B2 B3
A0 A1 A2 A3 B0 B1 B2 B3
L IA > B
OA > B
L IA < B #5 OA < B
H IA = B
OA = B
INPUTS
A19
B19
L
NOTE:
The SN54/74LS85 can be used as a 5-bit comparator
only when the outputs are used to drive the A0–A3 and
B0–B3 inputs of another SN54/74LS85 as shown in
Figure 2 in positions #1, 2, 3, and 4.
(MSB)
A20 A21 A22 A23 B20 B21 B22 B23
A0 A1 A2 A3 B0 B1 B2 B3
IA > B
OA > B
IA < B
#1 OA < B
IA = B
OA = B
NC
A5 A6 A7 A8 B5 B6 B7 B8
A0 A1 A2 A3 B0 B1 B2 B3
A4 IA > B
B4 IA < B
OA > B
#4 OA < B
L IA = B
OA = B NC
INPUTS
A10 A11 A12 A13 B10 B11 B12 B13
A0 A1 A2 A3 B0 B1 B2 B3
A9 IA > B
B9 IA < B
OA > B
#3 OA < B
L IA = B
OA = B NC
A15 A16 A17 A18 B15 B16 B17 B18
A0 A1 A2 A3 B0 B1 B2 B3
A14 IA > B
B14 IA < B
OA > B
#2 OA < B
L IA = B
OA = B NC
A0 A1 A2 A3 B0 B1 B2 B3
IA > B
OA > B
IA < B
#6 OA < B
IA = B
OA = B
MSB = MOST SIGNIFICANT BIT
LSB = LEAST SIGNIFICANT BIT
L = LOW LEVEL
H = HIGH LEVEL
NC = NO CONNECTION
Figure 2. Comparison of Two 24-Bit Words
FAST AND LS TTL DATA
5-86
OUTPUTS







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