BINARY COUNTER. SN54LS90 Datasheet 


DECADE COUNTER;
DIVIDEBYTWELVE COUNTER;
4BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are highspeed
4bit ripple type counters partitioned into two sections. Each counter has a di
videbytwo section and either a dividebyfive (LS90), dividebysix (LS92) or
dividebyeight (LS93) section which are triggered by a HIGHtoLOW transi
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, biquinary, modulo12, or modulo16 counters. All of
the counters have a 2input gated Master Reset (Clear), and the LS90 also
has a 2input gated Master Set (Preset 9).
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, BiQuinary, DividebyTwelve,
Binary
• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to
÷2 Section
Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
Clock (Active LOW going edge) Input to
÷8 Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset9, LS90) Inputs
Output from ÷2 Section (Notes b & c)
Outputs from ÷5 (LS90), ÷6 (LS92),
÷8 (LS93) Sections (Note b)
0.5 U.L.
1.5 U.L.
0.5 U.L.
2.0 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fanout plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LS90
67
12
MS
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
12
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
LOGIC SYMBOL
LS92
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
12
6 7 12 11 9 8
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
FAST AND LS TTL DATA
51
SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDEBYTWELVE COUNTER;
4BIT BINARY COUNTER
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 63208
14
1
N SUFFIX
PLASTIC
CASE 64606
14
1
D SUFFIX
SOIC
CASE 751A02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LS93
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
12
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13

SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LOGIC DIAGRAM
6
MS1
MS2 7
14
CP0
1
CP1
2
MR1
MR2 3
J SD Q
CP
K CD Q
12
Q0
LS90
J SD Q
CP
K CD Q
J SD Q
CP
K CD Q
R SD Q
CP
S CD Q
98
Q1 Q2
11
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
LS92
14
CP0
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
1
CP1
6
MR1
MR2 7
12
Q0
11
Q1
9
Q2
8
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
LS93
14
CP0
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
1
CP1
2
MR1
MR2 3
12
Q0
9 8 11
Q1 Q2 Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
FAST AND LS TTL DATA
52
CONNECTION DIAGRAM
DIP (TOP VIEW)
CP1 1
MR1 2
MR2 3
NC 4
VCC 5
MS1 6
MS2 7
14 CP0
13 NC
12 Q0
11 Q3
10 GND
9 Q1
8 Q2
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual InLine Package.
CONNECTION DIAGRAM
DIP (TOP VIEW)
CP1 1
NC 2
NC 3
NC 4
VCC 5
MR1 6
MR2 7
14 CP0
13 NC
12 Q0
11 Q1
10 GND
9 Q2
8 Q3
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual InLine Package.
CONNECTION DIAGRAM
DIP (TOP VIEW)
CP1 1
MR1 2
MR2 3
NC 4
VCC 5
NC 6
NC 7
14 CP0
13 NC
12 Q0
11 Q3
10 GND
9 Q1
8 Q2
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual InLine Package.

SN54/74LS90 • SN54/74LS92 • SN54/74LS93
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4bit ripple type Decade,
DivideByTwelve, and Binary Counters respectively. Each
device consists of four master/slave flipflops which are
internally connected to provide a dividebytwo section and a
dividebyfive (LS90), dividebysix (LS92), or dividebyeight
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGHtoLOW
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes. The Q0 output of
each device is designed and specified to drive the rated
fanout plus the CP1 input of the device.
A gated AND asynchronous Master Reset (MR1 • MR2) is
provided on all counters which overrides and clocks and
resets (clears) all the flipflops. A gated AND asynchronous
Master Set (MS1 • MS2) is provided on the LS90 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the dividebytwo section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes.
LS90
A. BCD Decade (8421) Counter — The CP1 input must be ex
ternally connected to the Q0 output. The CP0 input receives
the incoming count and a BCD count sequence is pro
duced.
B. Symmetrical Biquinary DivideByTen Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a divideby
ten square wave is obtained at output Q0.
C. DivideByTwo and DivideByFive Counter — No external
interconnections are required. The first flipflop is used as a
binary element for the dividebytwo function (CP0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary dividebyfive operation at the Q3 output.
LS92
A. Modulo 12, DivideByTwelve Counter — The CP1 input
must be externally connected to the Q0 output. The CP0 in
put receives the incoming count and Q3 produces a sym
metrical dividebytwelve square wave output.
B. DivideByTwo and DivideBySix Counter —No external
interconnections are required. The first flipflop is used as a
binary element for the dividebytwo function. The CP1 in
put is used to obtain dividebythree operation at the Q1
and Q2 outputs and dividebysix operation at the Q3 out
put.
LS93
A. 4Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
B. 3Bit Ripple Counter— The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flipflop is available if the reset function coin
cides with reset of the 3bit ripplethrough counter.
FAST AND LS TTL DATA
53

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