SMD84065013A Timer Datasheet pdf - Interval Timer. Equivalent, Catalog

82C54

March 1997

CMOS Programmable Interval Timer

Features

Description

• 8MHz to 12MHz Clock Input Frequency

• Compatible with NMOS 8254

- Enhanced Version of NMOS 8253

• Three Independent 16-Bit Counters

• Six Programmable Counter Modes

• Status Read Back Command

• Binary or BCD Counting

• Fully TTL Compatible

• Single 5V Power Supply

• Low Power

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz

• Operating Temperature Ranges

- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC

- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC

- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

The Intersil 82C54 is a high performance CMOS Program-

mable Interval Timer manufactured using an advanced 2

micron CMOS process.

The 82C54 has three independently programmable and

functional 16-bit counters, each capable of handling clock

input frequencies of up to 8MHz (82C54) or 10MHz

(82C54-10) or 12MHz (82C54-12).

The high speed and industry standard conﬁguration of the

82C54 make it compatible with the Intersil 80C86, 80C88,

and 80C286 CMOS microprocessors along with many other

industry standard processors. Six programmable timer

modes allow the 82C54 to be used as an event counter,

elapsed time indicator, programmable one-shot, and many

other applications. Static CMOS circuit design insures low

power operation.

The Intersil advanced CMOS process results in a signiﬁcant

reduction in power with performance equal to or greater than

existing equivalent products.

Pinouts

82C54 (PDIP, CERDIP, SOIC)

TOP VIEW

D7 1

D6 2

D5 3

D4 4

D3 5

D2 6

D1 7

D0 8

CLK 0 9

OUT 0 10

GATE 0 11

GND 12

24 VCC

23 WR

22 RD

21 CS

20 A1

19 A0

18 CLK 2

17 OUT 2

16 GATE 2

15 CLK 1

14 GATE 1

13 OUT 1

82C54 (PLCC/CLCC)

TOP VIEW

4 3 2 1 28 27 26

D4 5

D3 6

D2 7

D1 8

D0 9

CLK 0 10

NC 11

25 NC

24 CS

23 A1

22 A0

21 CLK2

20 OUT 2

19 GATE 2

12 13 14 15 16 17 18

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

4-1

File Number 2970.1

82C54

Ordering Information

8MHz

CP82C54

IP82C54

CS82C54

IS82C54

CD82C54

ID82C54

MD82C54/B

MR82C54/B

SMD # 8406501JA

SMD# 84065013A

CM82C54

PART NUMBERS

10MHz

CP82C54-10

IP82C54-10

CS82C54-10

IS82C54-10

CD82C54-10

ID82C54-10

MD82C54-10/B

MR82C54-10/B

CM82C54-10

Functional Diagram

12MHz

CP82C54-12

IP82C54-12

CS82C54-12

IS82C54-12

CD82C54-12

ID82C54-12

MD82C54-12/B

MR82C54-12/B

8406502JA

84065023A

CM82C54-12

TEMPERATURE

RANGE

0oC to +70oC

-40oC to +85oC

0oC to +70oC

-40oC to +85oC

0oC to +70oC

-40oC to +85oC

-55oC to +125oC

0oC to +70oC

PACKAGE

24 Lead PDIP

28 Lead PLCC

24 Lead CERDIP

28 Lead CLCC

24 Lead CERDIP

28 Lead CLCC

24 Lead SOIC

PKG. NO.

E24.6

N28.45

F24.6

J28.A

F24.6

J28.A

M24.3

D7 - D0 8

DATA/

BUS

BUFFER

READ/

WRITE

A0 LOGIC

CONTROL

WORD

Pin Description

SYMBOL

D7 - D0

CLK 0

OUT 0

GATE 0

GND

OUT 1

GATE 1

CLK 1

GATE 2

OUT 2

DIP PIN

NUMBER

1-8

COUNTER

CLK 0

GATE 0

OUT 0

CONTROL

WORD

CLK 1

GATE 1

OUT 1

CONTROL

LOGIC

STATUS

LATCH

STATUS

INTERNAL BUS

CRM

CRL

COUNTER

CLK 2

GATE 2

OUT 2

GATE n

CLK n OUT n

OLM

OLL

COUNTER INTERNAL BLOCK DIAGRAM

TYPE

I/O

DEFINITION

DATA: Bi-directional three-state data bus lines, connected to system data bus.

CLOCK 0: Clock input of Counter 0.

OUT 0: Output of Counter 0.

GATE 0: Gate input of Counter 0.

GROUND: Power supply connection.

OUT 1: Output of Counter 1.

GATE 1: Gate input of Counter 1.

CLOCK 1: Clock input of Counter 1.

GATE 2: Gate input of Counter 2.

OUT 2: Output of Counter 2.

4-2

82C54

Pin Description (Continued)

SYMBOL

CLK 2

A0, A1

DIP PIN

NUMBER

19 - 20

TYPE

DEFINITION

CLOCK 2: Clock input of Counter 2.

ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write

operations. Normally connected to the system address bus.

A1 A0

SELECTS

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

VCC

I CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and

WR are ignored otherwise.

I READ: This input is low during CPU read operations.

I WRITE: This input is low during CPU write operations.

VCC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended

for decoupling.

Functional Description

General

The 82C54 is a programmable interval timer/counter

designed for use with microcomputer systems. It is a general

purpose, multi-timing element that can be treated as an

array of I/O ports in the system software.

D7 - D0

DATA/

BUS

BUFFER

COUNTER

CLK 0

GATE 0

OUT 0

The 82C54 solves one of the most common problems in any

microcomputer system, the generation of accurate time

delays under software control. Instead of setting up timing

loops in software, the programmer conﬁgures the 82C54 to

match his requirements and programs one of the counters

for the desired delay. After the desired delay, the 82C54 will

interrupt the CPU. Software overhead is minimal and vari-

able length delays can easily be accommodated.

Some of the other computer/timer functions common to micro-

computers which can be implemented with the 82C54 are:

• Real time clock

• Event counter

• Digital one-shot

• Programmable rate generator

• Square wave generator

• Binary rate multiplier

• Complex waveform generator

• Complex motor controller

Data Bus Buffer

This three-state, bi-directional, 8-bit buffer is used to inter-

face the 82C54 to the system bus (see Figure 1).

READ/

WRITE

A0 LOGIC

CONTROL

WORD

COUNTER

CLK 1

GATE 1

OUT 1

COUNTER

CLK 2

GATE 2

OUT 2

FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC

FUNCTIONS

Read/Write Logic

The Read/Write Logic accepts inputs from the system bus and

generates control signals for the other functional blocks of the

82C54. A1 and A0 select one of the three counters or the Con-

trol Word Register to be read from/written into. A “low” on the

RD input tells the 82C54 that the CPU is reading one of the

counters. A “low” on the WR input tells the 82C54 that the CPU

is writing either a Control Word or an initial count. Both RD and

WR are qualiﬁed by CS; RD and WR are ignored unless the

82C54 has been selected by holding CS low.

4-3

Interval Timer. SMD84065013A Datasheet

SMD84065013A Timer. Datasheet pdf. Equivalent