Logic Array. PA7024 Datasheet

PA7024 Array. Datasheet pdf. Equivalent

Part PA7024
Description Programmable Electrically Erasable Logic Array
Feature Commercial/ Industrial PA7024 PA7024 PEELTM Array Programmable Electrically Erasable Logic Array F.
Manufacture ETC
Datasheet
Download PA7024 Datasheet



PA7024
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PA7024 PEELTM Array
Programmable Electrically Erasable Logic Array
Features
s CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
-Optional JN package for 22V10 power/ground
compatibility
s Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
s Flexible Logic Cell
- Multiple output functions per cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
-Sum of products logic for output enable
General Description
The PA7024 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free design-
ers from the limitations of ordinary PLDs by providing the
architectural flexibility and speed needed for today’s pro-
grammable logic designs. The PA7024 is by far the most
powerful 24-pin PLD available today with 20 I/O pins, 2
input/global-clocks and 40 registers/latches (20 buried logic
cells and 20 I/O registers/latches). Its logic array imple-
ments 84 sum-of-product logic functions that share 80
product terms. The PA7024’s logic and I/O cells (LCCs,
IOCs) are extremely flexible, offering two output functions
per logic cell (a total of 40 for all 20 logic cells). Logic cells
are configurable as D, T, and JK registers with independent
Figure 1: Pin Configuration
s High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V Vcc
and -40 to +85°C temperatures
s Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
s Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
-Programming support by ICT PDS-3 and popular third-
party programmers
or global clocks, resets, presets, clock polarity, and other
special features. This makes them suitable for a wide vari-
ety of combinatorial, synchronous and asynchronous logic
applications. With pin compatibility and super-set function-
ality to most 24-pin PLDs, (22V10, EP610/630, GAL6002),
the PA7024 can implement designs that exceed the archi-
tectures of such devices. The PA7024 supports speeds as
fast as 10ns/15ns (tpdi/tpdx) and 71.4MHz (fMAX) at mod-
erate power consumption 120mA (85mA typical). Packag-
ing includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). Development and programming support for the PA7024
is provided by ICT and popular third-party development tool
manufacturers.
Figure 2. Block Diagram
DIP
PLCC-J
SOIC
PLCC-JN
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PA7024
PA7024
Table 1. Absolute Maximum Ratings
Symbol
Parameter
VCC
VI, VO
IO
TST
TLT
Supply Voltage
Voltage Applied to Any Pin2
Output Current
Storage Temperature
Lead Temperature
Table 2. Operating Ranges
This device has been designed and tested for the recommended
operating conditions. Proper operation outside these levels is not
guaranteed. Exposure to absolute maximum ratings may cause per-
manent damage.
Conditions
Ratings
Unit
Relative to Ground
Relative to Ground1
Per pin (IOL, IOH)
-0.5 to + 7.0
-0.5 to VCC + 0.6
±25
-65 to + 150
V
V
mA
°C
Soldering 10 seconds
+300
°C
Symbol
Parameter
Conditions
Min Max
VCC
Supply Voltage
Commercial
Industrial
4.75 5.25
4.5 5.5
Commercial
TA Ambient Temperature
Industrial
TR Clock Rise Time
See Note 2
0 +70
-40 +85
20
TF
TRVCC
Clock Fall Time
VCC Rise Time
See Note 2
See Note 2
20
250
Table 3. D.C. Electrical Characteristics over the recommended operating conditions
Unit
V
°C
ns
ns
ms
Symbol
VOH
VOHC
VOL
VOLC
VIH
VIL
IIL
IOZ
ISC
ICC11
CIN7
COUT7
Parameter
Output HIGH Voltage - TTL
Output HIGH Voltage - CMOS
Output LOW Voltage - TTL
Output LOW Voltage - CMOS
Input HIGH Level
Input LOW Level
Input Leakage Current
Output Leakage Current
Output Short Circuit Current4
VCC Current
Input Capacitance5
Output Capacitance5
Conditions
VCC = Min, IOH = -4.0mA
VCC = Min, IOH = -10µA
VCC = Min, IOL = 16mA
VCC = Min, IOL = 10µA
VCC = Max, GND VIN VCC
I/O = High-Z, GND VO VCC
VCC = 5V, VO = 0.5V, TA= 25°C
VIN = 0V or VCC3,11
f = 25MHz
All outputs disabled4
-15
-20
-25
I-25
TA = 25°C, VCC = 5.0V
@ f = 1 MHz
Min
2.4
VCC - 0.3
2.0
-0.3
-30
85 (typ.)17
Max
0.5
0.15
VCC + 0.3
0.8
±10
±10
-120
120
120
120
130
6
12
Unit
V
V
V
V
V
V
µA
µA
mA
mA
pF
pF
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