Erasable Logic. PA7540 Datasheet

PA7540 Logic. Datasheet pdf. Equivalent

PA7540 Datasheet
Recommendation PA7540 Datasheet
Part PA7540
Description PA7540 PEEL Array Programmable Electrically Erasable Logic
Feature PA7540; PA7540 PEEL Array™ Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available.
Manufacture ETC
Datasheet
Download PA7540 Datasheet




ETC PA7540
PA7540 PEEL Array™
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide-
gate functions
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
General Description
The PA7540 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7540 is by far
the most powerful 24-pin PLD available today with 20 I/O
pins, 2 input/global-clocks and 40 registers/latches (20
buried logic cells and 20 I/O registers/latches). Its logic
array implements 84 sum-of-products logic functions. The
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely
flexible offering two output functions per cell (a total of 40
for all 20 logic cells). Logic cells are configurable as D, T,
and JK registers with independent or global clocks, resets,
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- Anachip’s WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
presets, clock polarity, and other features, making the
PA7540 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. With pin
compatibility and super-set functionality to most 24-pin
PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
implement designs that exceed the architectures of such
devices. The PA7540 supports speeds as fast as
10ns/15ns (tpdi/tpdx) and 71.46MHz (fMAX) at moderate
power consumption 80mA (55mA typical). Packaging
includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). Anachip and popular third-party development tool
manufacturers provide development and programming
support for the PA7540.
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
DIP
1
2
3
4
5
6
7
8
9
10
11
12
24
VCC
I/CLK1
23 I/O
22 I/O
I/O
I/O
I/O
21 I/O
I/O
20 I/O
19 I/O
I/O
I/O
I/O
18 I/O
I/O
17 I/O
16 I/O
I/O
I/O
GND
15 I/O
14 I/O
13 I/CLK2
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/CLK2
S O IC
4 3 2 1 28 27 26
I/O 5
25
I/O 6
24
I/O 7
23
NC 8
22
I/O 9
21
I/O 10
20
I/O 11
19
12 13 14 15 16 1718
P L C C -J
I/O I/O
I/O I/O
I/O I/O
NC NC
I/O I/O
I/O I/O
I/O I/O
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/O
I/O
I/O
NC
I/O
I/O
I/O
P L C C -J N
08-14-001B
2 Input/
Global Clock Pins
I/C L K 1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
G lobal C ells
I/O Cells
PA7540
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C L K 2
Logic Control C ells
G lo b al
C e lls
84 (42X2)
Array Inputs
true and
2 com plem ent
20
I/O
C e lls
(IO C )
20 I/O P ins
Logic
Array
20 Buried
logic
Logic
A
B
C o ntro l
C Cells
D (LCC)
20
Logic functions
to I/O cells
4 sum term s
4 product term s
for Global Cells
80 sum terms
(four per LCC)
20
20 Logic Control Cells
2 output functions per cell
(40 total output functions possible)
08-14-002A
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ETC PA7540
Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7540 PEEL™ Array, 42 inputs are
available into the array from the I/O cells and input/global-
clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7540 PEEL™ Arrays contains 84 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
From
IO C ells
(IO C) and
I/C L K s
42 Array Inputs
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can be
used for clocks, resets, presets and output enables instead of
just simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL™ logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From Global Cell
System C lock
Preset RegType Reset
From
Logic
Control
C e lls
(LCC)
MUX
O n/O ff
P
D ,T,J
Q
REG
K
R
MUX
To
Array
To
G lobal
C e lls
84 Product Terms
To
Logic C ontrol
C e lls
(LCC)
From
Array
A
B
C
D
MUX
To
I/O
C e ll
0 8 -1 4 -0 0 4 A
PA7540 Logic Array
84 Sum Terms
Figure 3 PA7540 Logic Array
0 8- 1 4 -0 0 3 A
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
ensures that product-terms are used where they are
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
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ETC PA7540
Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable
P
DQ
R
D Register
Q = D after clocked
Best for storage, simple counters,
shifters and state machines with
few hold (loop) conditions.
P
TQ
R
T Register
Q toggles when T = 1
Q holds when T = 0
Best for wide binary counters (saves
product terms) and state machines
with many hold (loop) conditions.
P
JQ
KR
JK Register
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q = 1 when J/K = 1/0
Q = 0 when J/K = 0/1
Combines features of both D and T
registers.
08-14-005A
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register or the output
enable for the connected I/O cell. Note that the sums
controlling clocks, resets, presets and output enables are
complete sum-of-product functions, not just product terms
as with most other PLDs. This also means that any input or
I/O pin can be used as a clock or other control function.
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 10).
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one output can be combinatorial and the
third, an output enable. The multi-function PEEL™ Array logic
cells are equivalent to two or three macrocells of other PLDs,
which have only one output per cell. They also allow registers
to be truly buried from I/O pins without limiting them to input-
only (see Figure 8 ).
From Global Cell
I/O Cell Clock
To
Array
Input
MUX
REG/
Latch
Q
From
Logic
Control
Cell
A,B,C
or
Q
D
MUX
MUX
10
7540 /O Cell (IOC)
Figure 6. I/O Cell Block Diagram
I/O Pin
08-14-006A
D Q IO C R egister
Q = D after rising edge of clock
holds until next rising edge
L Q IO C Latch
Q = L when clock is high
holds value when clock is low
08-14-007A
Figure 7. IOC Register Configurations
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the LCCs
in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-state
buffer and an output polarity control. The register/ latch can
be clocked from a variety of sources determined by the global
cell. It can also be bypassed for a non-registered input. The
combination of LCC and IOC allows for multiple buried
registers and logic paths. (See Figure 8).
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