PROTECTION ARRAYS. PACDN1404C Datasheet

PACDN1404C ARRAYS. Datasheet pdf. Equivalent

Part PACDN1404C
Description ESD PROTECTION ARRAYS
Feature CALIFORNIA MICRO DEVICES PACDN1404C PACDN1408C PACDN1416C ESD Protection Arrays, Chip Scale Packag.
Manufacture California Micro Devices Corp
Datasheet
Download PACDN1404C Datasheet

CALIFORNIA MICRO DEVICES PACDN1404C PACDN1408C PACDN1416C PACDN1404C Datasheet
Recommendation Recommendation Datasheet PACDN1404C Datasheet





PACDN1404C
CALIFORNIA MICRO DEVICES
PACDN1404C
PACDN1408C
PACDN1416C
ESD Protection Arrays, Chip Scale Package
Features
• 4, 8, or 16 transient voltage suppressors in a
single package
• In-system Electrostatic Discharge (ESD)
protection to 25kV contact discharge per
IEC 61000-4-2 international standard
• Compact Chip Scale Package (0.65mm pitch) format
saves board space and eases layout in space
critical applications compared to discrete
solutions and traditional wire bonded packages
Applications
• ESD protection of I/O port connections,
such as cellular phone, PDA, internet appliance
and PC ports
• Protection of interface ports or IC pins which are
exposed to high levels of ESD
Product Description
The PACDN1404C, PACDN1408C and PACDN1416C
are transient voltage suppressor arrays that provide a
very high level of protection for sensitive electronic
components that may be subjected to ESD.
These devices are designed and characterized to safely
dissipate ESD strikes at levels well beyond the maxi-
mum requirements set forth in the IEC 61000-4-2
international standard (Level 4, 8kV contact discharge).
All I/Os are rated at 25kV using the IEC 61000-4-2
contact discharge method. Using the MIL-STD-883D
(Method 3015) specification for Human Body Model
(HBM) ESD, all pins are protected for contact discharges
to greater than 30kV.
The Chip Scale Package format of these devices enable
extremely small footprints that are necessary in portable
electronics such as cellular phones, PDAs, internet
appliances and PCs. The large solder bumps allow for
standard attachment to laminate boards without the use
of underfill.
SCHEMATIC DIAGRAMS
D1 D2 D3
D4 D5
B1 B2 B3
A1 A2 A3
PACDN1404C
B1 B2 B3 B4 B5
A1 A2 A3 A4 A5
PACDN1408C
C1 C2 C3
B1 B2 B3
C4 C5
B4 B5
A1 A2 A3
A4 A5
PACDN1416C
Package
Style
Chip Scale
Chip Scale
Chip Scale
STANDARD PART ORDERING INFORMATION
Ordering Part Number
Bumps
Tape & Reel
6 PACDN1404C/R
10 PACDN1408C/R
20 PACDN1416C/R
© 2000 California Micro Devices Corp. All rights reserved.
8/4/2000 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
C1230700
www.calmicro.com
1



PACDN1404C
CALIFORNIA MICRO DEVICES
PACDN1404C
PACDN1408C
PACDN1416C
S P E C I F I C AT I O N S
(At 25°C unless specified otherwise)
Reverse Stand-off Voltage, I = 10µA
Min Typ Max Unit
5.5 V
Signal Clamp Voltage:
Positive Clamp, 10mA
Negative Clamp, 10mA
5.6
1.2
6.6
0.8
8.0
0.4
V
V
In-system ESD withstand voltage*:
Human Body Model (MIL-STD-883D, method 3015)
IEC 61000-4-2, contact discharge method
±30 kV
±25 kV
Clamping voltage during ESD discharge
MIL-STD-883D (Method 3015), 8kV
Positive
Negative
12 V
8 V
Capacitance at 2.5V dc, 1MHz
Temperature Range:
Operating
Storage
39 pF
40 85 °C
65 150
* ESD applied between channel pin and ground, one at a time. All other channels are open. All GND pins grounded. This
parameter is guaranteed by design and characterization.
GNDin this document refers to the lower supply voltage.
PRINTED CIRCUIT BOARD RECOMMENDATIONS
Pad Size on PCB
0.300mm
Pad Shape
Round
Pad Definition
Non Solder Mask Defined Pads (NSMD)
Solder Mask Opening
0.350mm
Solder Stencil Thickness
0.152mm
Solder Stencil Aperture Opening
0.360mm (sq.)
Solder Flux Ratio
50/50
Solder Paste
No Clean
Bond Trace Finish
OSP (Entek Cu Plus 106A)
250
EXH
225
200
175
150
125
100
75
50
25
0
PH
48
Z2 Z3 Z4
Z5 RF
CD
EXH
97 145 194 242 290 339 387 435
Time (s)
Typical Solder Reflow Thermal Profile (No Clean Flux)
©2000 California Micro Devices Corp. All rights reserved.
2 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com 8/4/2000





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