TERMINATION NETWORK. PACS1284 Datasheet

PACS1284 NETWORK. Datasheet pdf. Equivalent

PACS1284 Datasheet
Recommendation PACS1284 Datasheet
Part PACS1284
Description IEEE 1284 ECP/EPP TERMINATION NETWORK
Feature PACS1284; CALIFORNIA MICRO DEVICES PACS1284 P/Active™ IEEE 1284 ECP/EPP Termination Network Features • Sing.
Manufacture California Micro Devices Corp
Datasheet
Download PACS1284 Datasheet




California Micro Devices Corp PACS1284
CALIFORNIA MICRO DEVICES
PACS1284
P/Active™ IEEE 1284 ECP/EPP Termination Network
Features
• Single chip IEEE 1284 parallel port termination
• 28 pin QSOP package, smallest physical solution
• 17 terminating lines in a single package
• In system ESD protection to 8KV, HBM
• In system ESD protection to 4KV per IEC1000-4-2
• Protects downstream devices to 30V
Applications
• ECP/EPP Parallel Port termination
• PC Peripherals
• Notebook and Desktop computers
• Engineering Workstations and Servers
Product Description
California Micro Devices’ PACS1284 Parallel Port
Termination Network provides a complete integrated
solution for the entire IEEE 1284 interface in a single
QSOP package.
Advanced, enhanced high-speed parallel ports, con-
forming to the IEEE 1284 standard, are used to provide
communications with external devices such as tape
back-up drives, ZIP drives, printers, parallel port SCSI
adapters, external LAN adapters, scanners, video
capture, and other PC peripherals. These advanced
ports support bi-directional transfers to 2MB/sec. To
effectively support these higher transfer data rates, the
IEEE 1284 standard recommends a combined termina-
tion, pull-up filter network between the driver/receiver
and the cable at both ends of the parallel port interface.
In addition, government EMC compatibility requirements
impose strict filtering on the parallel port. California
Micro Devices’ PACS1284 Parallel Port Termination
Network addresses all of these requirements by provid-
ing a seventeen line, IEEE 1284 compliant network in a
thin film integrated circuit. The device provides a com-
plete parallel port termination solution for space critical
applications by integrating a total of 43 discrete compo-
nents. In addition, all I/O pins are ESD protected for
contact discharges up to 4KV per the Human Body
Model. However, the output pins of the device which
have the highest probability of exposure to ESD pulses
are protected to 8KV, HBM, thereby providing the
necessary robustness for the port’s application environ-
ment.
California Micro Devices’ P/Active technology provides
high reliability and low cost through manufacturing
efficiency. The resistors and capacitors are fabricated
using proprietary state-of-the-art thin film technology.
California Micro Devices’ solution is silicon-based and
has the same reliability characteristics as today’s
integrated circuits.
SCHEMATIC CONFIGURATION
GND
VCC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R1 R1 R1 R1 R1 R1 R1 R1
R1
R1 R1
R1 R1
R1 R1 R1 R1
R2 R2 R2 R2
R2
R2
R2 R2 R2
CC C CC C C C
C
CC
CC
CC C C
12
34 5 6
78
9 10
11 12
13 14
RC Code
02
04
Package
Pins
28
28
STANDARD PART ORDERING INFORMATION
Ordering Part Number
Style
Tubes
Tape & Reel
QSOP
PACS1284-02Q/T
PACS1284-02Q/R
QSOP
PACS1284-04Q/T
PACS1284-04Q/R
© 2000 California Micro Devices Corp. All rights reserved.
8/25/2000 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
Part Marking
PACS128402Q
PACS128404Q
C1420800
www.calmicro.com
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California Micro Devices Corp PACS1284
CALIFORNIA MICRO DEVICES
PACS1284
STANDARD SPECIFICATIONS
Absolute Tolerance (R)
±10%
Absolute Tolerance (C)
±20%
Operating Temperature Range 0°C to 70°C
VCC
Power Rating/Resistor
6V Max
100mW
Maximum Leakage Current
(at VCC Max)
Signal Clamp Voltage:
Positive Clamp
Negative Clamp
1µA@25° C
>6V
<6V
Storage Temperature
65°C to 150°C
Package Power Rating
1.00W, Max
R1()
2.2K
4.7K
STANDARD VALUES
R2()
c(Pf)
33 220
33 180
RC Code
02
04
ESD SPECIFICATIONS
ESD Protection*
Peak Discharge Voltage at any I/O, Human Body Model, Method 3015 (Note 1)
In System Protection, HBM (Note 2)
In System Protection, IEC 1000-4-2, Level 2 (Note 1, 2)
Channel Clamp Voltage @ 8KV ESD Pulses, HBM (Note 1, 2)
Min
4KV
8KV
4KV
30V
Max
4KV
8KV
4KV
30V
* Guaranteed by design
Note 1: Human Body Model per MIL-STD-883, Method 3015
CDischarge = 100pF, RDischarge = 1.5 K, pin 20 @ 5V and pin 22 @ ground.
ESD Contact Discharge from I/O pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23 through 28 to ground (pin22), one at a time.
Note 2: Pin 22 grounded, pin 20 to VCC, all other pins are open. ESD contact discharge between ground and
pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23 through 28, one at a time.
Note 3: Standard IEC 1000-4-2 with CDischarge = 150pF, RDischarge = 330, pin 20 @ 5V and pin 22 @ ground.
©2000 California Micro Devices Corp. All rights reserved.
2 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com 8/25/2000



California Micro Devices Corp PACS1284
CALIFORNIA MICRO DEVICES
PACS1284
Application Information
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and
Status lines (8 in total) only require a pull-up resistor and a filter capacitor. The Data lines and Strobe also require a
series termination resistor in addition to the pull resistors and filter capacitors. See Table 1 and Schematic Diagram.
Signal Name
Data1 - Data8
Strobe
Init
AutoFeedXT
Selectin
Ack
Busy
Paper Empty
Select
Fault
Series Termination
Yes
Yes
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Table 1.
IEEE 1284 defines three interface connectors:
1284-A is a 25-pin DB series connector which is the defacto PC standard for the host connection.
1284-B is a 36-pin, 0.085 inch centerline connector used on the peripheral device.
1284-C is a new 36-pin, 0.050 inch centerline connector which can be used for both host and peripheral.
Figure 1 shows a possible hook-up between the 1284-A connector on a PC motherboard and the PACS1284, illustrat-
ing how the pin configuration of the PACS1284 allows for easy interconnects between the two. The dotted I/O signals
of the PACS1284 will typically be connected to a Super I/O chip on the motherboard.
Figure 2 shows a possible hook-up between the 1284-B connector on a peripheral and the PACS1284.
Figure 3 shows a possible hook-up between the 1284-C connector and the PACS1284.
1284-A Connector
Host
14 25
1 13
1284-B Connector
Peripheral
19
1
36
18
1284-C Connector
Host/Peripheral
20
19
2
1
36
18
SUPER 1284
1
= FLOW
THROUGH
SIGNALS
SUPER 1284
1
= GND
= VCC
SUPER 1284
1
Figure 1.
Figure 2.
Figure 3.
Sample Hook-ups of IEEE 1284 Connectors and PACS1284.
(connector and PACS1284 not drawn to scale)
© 2000 California Micro Devices Corp. All rights reserved.
8/25/2000 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3





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