COMPANION CIRCUIT. PACVGA201 Datasheet

PACVGA201 CIRCUIT. Datasheet pdf. Equivalent

Part PACVGA201
Description VGA PORT COMPANION CIRCUIT
Feature CALIFORNIA MICRO DEVICES VGA PORT COMPANION CIRCUIT Features • 7 channels of ESD protection for al.
Manufacture California Micro Devices Corp
Datasheet
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PACVGA201
CALIFORNIA MICRO DEVICES
VGA PORT COMPANION CIRCUIT
Features
• 7 channels of ESD protection for all VGA port
connector pins meeting IEC-61000-4-2 Level-4 ESD
requirements (8KV contact discharge)
• Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
• TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
• Three power supplies for design flexibility
• Compact 16-pin QSOP package
Pin Diagram
PACVGA201
16-PIN QSOP PACKAGE
Product Description
The PACVGA201 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low
voltage video controller ICs and provide design flexibility in multiple-supply-voltage environments.
An internal diode (D1, in schematic below) is provided such that VCC2 is derived from VCC3. (VCC2 does not require an external
power supply input.) In applications where VCC3 may be powered down, diode D1 blocks any DC current path from the
DDC_OUT pins back to the powered down VCC3 rail via the upper ESD protection diodes.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC3.
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current
from the VCC3 supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.
Schematic Diagram
© 2000 California Micro Devices Corp. All rights reserved. PAC VGA201™ is a trademark of California Micro Devices Corp.
4/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
C0651299
1



PACVGA201
CALIFORNIA MICRO DEVICES
PACVGA201
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
VCC1, VCC3 supply voltage
DC voltage at inputs:
GND-0.5, +6.0
VIDEO_1, VIDEO_2, VIDEO_3
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
Temperature:
GND-0.5, VCC1+0.5
GND-0.5, VCC2+0.5
GND-0.5, VCC3+0.5
Storage
-40 to +150
Operating Ambient
0 to +70
Package power dissipation
0.75
Unit
V
V
V
V
V
oC
oC
W
Symbol
ICC1
ICC3
VCC2
V IH
V IL
V OH
VOL
Rb, Rp
IN
CIN
tPLH
tPHL
tr, tf
VESD
ELECTRICAL OPERATING CHARACTERISTICS
(over operating conditions unless specified otherwise)
Parameter
Conditions
MIN
VCC1 supply current
VCC3 supply current
VCC1 = 5V
VCC3 = 5V; SYNC inputs at GND or VCC3;
PWR_UP pin at VCC3; SYNC outputs unloaded
VCC3 = 5V; SYNC inputs at 3.0V; PWR_UP
pin at VCC3; SYNC outputs unloaded
VCC3 = 5V; PWR_UP input at GND; SYNC
outputs unloaded
VCC2 pin open circuit voltage
VCC2 voltage internally derived from VCC3 via
diode D1; no external current drawn;
Logic High input voltage1
Logic Low input voltage1
Logic High output voltage2
Logic Low output voltage2
Resistor value
Input current
VCC3 = 5.0V
VCC3 = 5.0V
IOH = -4mA, VCC3 = 5.0V
IOL = 4mA, VCC3 = 5.0V
PWR_UP, VCC3 = 5.0V
2.0
4.4
0.5
VIDEO inputs
HSYNC, VSYNC inputs
Input capacitance 4
VCC1 = 5V; VIN = VCC1 or GND
VCC3 = 5V; VIN = VCC3 or GND
VIDEO_1, VIDEO_2, VIDEO_3
SYNC drivers L-H propagation delay
SYNC drivers H-L propagation delay
SYNC drivers output rise & fall times
ESD withstand voltage3, 4
VCC1 = 5.0V; VIN = 2.5V; measured at 1MHz
VCC1 = 2.5V; VIN = 1.25V; measured at 1MHz
CL = 50 pF; VCC3 = 5V; Input tr and tf < 5ns
CL = 50 pF; VCC3 = 5V; Input tr and tf < 5ns
CL = 50 pF; VCC3 = 5V; Input tr and tf < 5ns
VCC1 = VCC2 = VCC3 = 5V
±8
TYP
10
200
VCC3-0.8
1
4.0
4.5
8
8
7
MAX
10
10
0.8
0.4
2
±1
±1
12
12
UNIT
uA
uA
uA
uA
V
V
V
V
V
M
µA
µA
pF
ns
ns
ns
kV
Note 1:
Note 2:
Note 3:
Note 4:
These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP.
These parameters apply only to SYNC_OUT1 and SYNC_OUT2.
Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC2 and VCC3 must be bypassed to GND via
a low impedance ground plane with a 0.2uF or greater, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied
between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1,
VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the
industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
This parameter is guaranteed by design and characterization.
©2000 California Micro Devices Corp. All rights reserved.
2 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
4/00





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