1P AL CE 20 V8 fax id: 6010 PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL® Device Features • Active pull-up on data input pins • Low power version (20V8L) — 55 mA max. commercial (15, 25 ns) — 65 mA max. military/industrial (15, 25 ns) • Standard version has low power — 90 mA max. commercial (15, 25 ns) — 115 mA max. commercial (10 ns) — 130 mA max. military/industrial (15, 25 ns) • CMOS Flash technology for electrical erasability and reprogrammability • User-programmable macrocell — Output polarity control — Individually selectable for registered or combinatorial operation • QSOP package available — 10, 15, and 25 ns com’l version — 15, and 25 ns military/industrial versions • High reliability — Proven Flash technology — 100% programming and functional testing Functional Description The Cypress PALCE20V8 is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. The PALCE20V8 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerdip, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and a 24-lead quarter size outline. The device provides up to 20 inputs and 8 outputs. The PALCE20V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 24-pin PLDs such as 20L8, 20R8, 20R6, 20R4. Logic Block Diagram (PDIP/CDIP/QSOP) GND 12 I10 11 I9 10 I8 9 I7 8 I6 7 I5 6 I4 5 I3 4 I2 3 I1 2 CLK/I0 1 PROGRAMMABLE AND ARRAY (64 x 40) 8 8 8 8 8 8 8 8 MUX Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell MUX 13 OE/I11 14 I12 15 I/O0 16 I/O1 17 I/O2 18 I/O3 19 I/O4 20 I/O5 21 I/O6 22 I/O7 23 I13 24 VCC 20V8–1 PAL is a registered trademark of Advanced Micro Devices, Inc. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 1994 – Revised March 26, 1997 PALCE20V8 Pin Configuration DIP/QSOP Top View CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I13 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I12 OE/I11 20V8–2 PLCC/LCC Top View 4 3 2 1 2827 26 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O6 I/O5 I/O4 NC I/O3 I/O2 I/O1 20V8–3 121314 1516 1718 Selection Guide tPD ns Generic Part Number PALCE20V8−5 PALCE20V8−7 PALCE20V8−10 PALCE20V8−15 PALCE20V8−25 PALCE20V8L−15 PALCE20V8L−25 Com’l/Ind 5 7.5 10 15 25 15 25 10 15 25 15 25 Mil 3 7 10 12 15 12 15 10 12 20 12 20 tS ns Com’l/Ind Mil 4 5 7 10 12 10 12 10 12 20 12 20 tCO ns Com’l/Ind Mil 115 115 115 90 90 55 55 130 130 130 65 65 ICC mA Com’l Mil/Ind Shaded area contains preliminary information. Functional Description (continued) The PALCE20V8 features 8 product terms per output and 40 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control or as a data product term. There are a total of 18 architecture bits in the PALCE20V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself. Power-Up Reset All registers in the PALCE20V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. Electronic Signature An electronic signature word is provided in the PALCE20V8 that consists of 64 bits of programmable memory that can contain user-defined data. Security Bit A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. Low Power The Cypress PALCE20V8 provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled. Input and I/O Pin Pull-Ups The PALCE20V8 input and I/O pins have built-in active pull-ups that will float unused inputs and I/Os to an active HIGH state (logical 1). All unused inputs and three-stated I/O pins should be connected to another active input, VCC, or Ground to improve noise immunity and reduce ICC. 2 PALCE20V8 Configuration Table CG0 0 0 1 1 1 CG1 1 1 0 0 1 CL0x 0 1 0 1 1 Cell Configuration Registered Output Combinatorial I/O Combinatorial Output Input Combinatorial I/O Devices Emulated Registered Med PALs Registered Med PALs Small PALs Small PALs 20L8 only Macrocell 1 1 1 0 0 0 0 1 To Adjacent Macrocell 1 1 0 X 1 0 OE VCC CG1 CL0x 1 1 0 X D Q Q 1 0 1 1 0 X CG1 for pin 16 to 21 (DIP) CG0 for pin 15 and 22 (DIP) CL0x 1 0 I/Ox VCC CLK CL1x From Adjacent Pin 20V8–4 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................− 0.5V to +7.0V DC Input Voltage .................................................−0.5V to +7.0V Output Current into Outputs (LOW)............................. 24 mA DC Programming Voltage............................................. 12.5V Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Military[1] Ambient Temperature 0°C to +75°C −40°C to +85°C −55°C to +125°C VCC 5V ±5% 5V ±10% 5V ±10% Note: 1. TA is the “instant on” case temperature. 3 PALCE20V8 Electrical Characteristics Over the Operating Range[2] Parameter VOH VOL VIH VIL[4] IIH IIL[5] ISC ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input or I/O HIGH Leakage Current Input or I/O LOW Leakage Current Operating Power Supply Current VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL Test Conditions IOH = −3.2 mA IOH = −2 mA IOL = 24 mA IOL = 12 mA Com’l Mil/Ind Com’l Mil/Ind 2.0 −0.5 0.8 10 −100 −30 Com’l −150 115 90 55 Mil/Ind Mil/Ind 130 65 V V µA µA mA mA mA mA mA mA 0.5 V Min. 2.4 Max. Unit V Guaranteed Input Logical HIGH Voltage for All Inputs[3] Guaranteed Input Logical LOW Voltage for All Inputs[3] 3.5V < VIN < VCC 0V < VIN < VIN (Max.) Output Short Circuit Current VCC = Max., VOUT = 0.5V[6,7] VCC = Max., VIL = 0V, VIH = 3V, Output Open, f = 15 MHz (counter) 5, 7, 10 ns 15, 25 ns 15L, 25L ns 10, 15, 25 ns 15L, 25L ns Capacitance[7] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0V @ f = 1 MHz VOUT = 2.0V @ f = 1 MHz Typ. 5 5 Unit pF pF Endurance Characteristics[7] Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions Min. 100 Max. Unit Cycles Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to −3.0V for pulse durations less than 20 ns. 5. The leakage current is due to the internal pull-up resistor on all pins. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. 4 PALCE20V8 AC Test Loads and Waveforms ALL INPUT PULSES 3.0V 90% GND ≤ 2 ns 10% 90% 10% ≤ 2 ns 20V8–5 5V S1 R1 OUTPUT R2 CL 20V8–6 TEST POINT Commercial Specification tPD, tCO tPZX, tEA tPXZ, tER Closed Z ± H: Open Z ± L: Closed H ± Z: Open L ± Z: Closed 5 pF S1 CL 50 pF R1 200Ω R2 390Ω R1 Military R2 750Ω Measured Output Value 1.5V 1.5V H ± Z: VOH − 0.5V L ± Z: VOL + 0.5V 390Ω 5 PALCE20V8 Commercial and Industrial Switching Characteristics[2] 20V8−5 Parameter tPD tPZX tPXZ tEA tER tCO tS tH tP tWH tWL fMAX1 fMAX2 Description Input to Output Propagation Delay[8] OE to Output Enable OE to Output Disable Input to Output Enable Delay[7] Input to Output Disable Delay[7,9] Clock to Output Delay[8] Input or Feedback Set-Up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH[7] Clock Width LOW [7] External Maximum Frequency (1/(tCO + tS))[7,10] Data Path Maximum Frequency (1/(tWH + tWL))[7, 11] Internal Feedback Maximum Frequency (1/(tCF + tS))[7,12] Register Clock to Feedback Input[7, 13] Power-Up Reset Time[7] 1 1 3 0 7 3 3 143 166. 6 166. 6 3 1 Min. 1 Max. 5 5 5 6 6 4 1 7 0 12 5 5 83 100 20V8−7 Min. 1 Max. 7.5 6 6 9 9 5 1 10 0 17 8 8 58 62.5 20V8−10 Min. 1 Max. 10 10 10 10 10 7 1 12 0 22 8 8 45.5 62.5 20V8−15 Min. 1 Max. 15 15 15 15 15 10 1 15 0 27 12 12 37 41.6 20V8−25 Min. 1 Max. 25 20 20 25 25 12 Unit ns ns ns ns ns ns ns ns ns ns ns MHz MHz fMAX3 tCF tPR 100 3 62.5 6 1 50 8 1 40 10 1 MHz ns µs Shaded area contains preliminary information. Notes: 8. Min. times are tested initially and after any design or proc PAL20V8 Device Datasheet pdf - PAL Device. Equivalent, Catalog

PAL Device. PAL20V8 Datasheet

PAL20V8 Device. Datasheet pdf. Equivalent

PAL20V8 Datasheet
Recommendation PAL20V8 Datasheet
Part PAL20V8
Description Flash Erasable/ Reprogrammable CMOS PAL Device
Feature PAL20V8; 1P AL CE 20 V8 fax id: 6010 PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL® Device Features • .
Manufacture Cypress Semiconductor
Datasheet
Download PAL20V8 Datasheet





Cypress Semiconductor PAL20V8
1P AL CE 20 V8
fax id: 6010
PALCE20V8
Flash Erasable,
Reprogrammable CMOS PAL® Device
Features
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
— 65 mA max. military/industrial
(15, 25 ns)
• QSOP package available
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
• High reliability
— Proven Flash technology
— 100% programming and functional testing
• Standard version has low power
— 90 mA max. commercial
(15, 25 ns)
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.
Logic Block Diagram (PDIP/CDIP/QSOP)
GND
12
I10
11
I9
10
I8 I7 I6
9 87
I5 I4
65
I3 I2 I1 CLK/I0
4 3 21
PROGRAMMABLE
AND ARRAY
(64 x 40)
8 8 8 88 8 8
8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
MUX
13 14
15
16
17
18
OE/I11
I12
I/O0
I/O1
I/O2
I/O3
PAL is a registered trademark of Advanced Micro Devices, Inc.
19
I/O4
20 21 22 23 24
I/O5 I/O6 I/O7 I13 VCC
20V8–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 1994 – Revised March 26, 1997



Cypress Semiconductor PAL20V8
PALCE20V8
Pin Configuration
DIP/QSOP
Top View
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I13
22 I/O7
21 I/O6
20 I/O5
19 I/O4
18 I/O3
17 I/O2
16 I/O1
15 I/O0
14 I12
13 OE/I11
20V8–2
PLCC/LCC
Top View
4 3 2 1 2827 26
I3 5
25 I/O6
I4 6
24 I/O5
I5 7
23 I/O4
NC 8
22 NC
I6 9
21 I/O3
I7 10
20 I/O2
I8
11
121314
1516 1718 19
I/O1
20V8–3
Selection Guide
Generic Part Number
tPD ns
Com’l/Ind Mil
PALCE20V85
PALCE20V87
5
7.5
PALCE20V810
10 10
PALCE20V815
15 15
PALCE20V825
25 25
PALCE20V8L15
15 15
PALCE20V8L25
25 25
Shaded area contains preliminary information.
tS ns
Com’l/Ind Mil
3
7
10 10
12 12
15 20
12 12
15 20
tCO ns
Com’l/Ind Mil
4
5
7 10
10 12
12 20
10 12
12 20
ICC mA
Com’l Mil/Ind
115
115
115 130
90 130
90 130
55 65
55 65
Functional Description (continued)
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, VCC, or
Ground to improve noise immunity and reduce ICC.
2



Cypress Semiconductor PAL20V8
PALCE20V8
Configuration Table
CG0
0
0
1
1
1
CG1
1
1
0
0
1
CL0x
0
1
0
1
1
Cell Configuration
Registered Output
Combinatorial I/O
Combinatorial Output
Input
Combinatorial I/O
Macrocell
Devices Emulated
Registered Med PALs
Registered Med PALs
Small PALs
Small PALs
20L8 only
1 1 To
11
OE
VCC
10
00
Adjacent
Macrocell
0X 01
10
CL0x
CG1
DQ
VCC
CLK Q
11
0X
10
CL1x
10
11
0X
CG1 for pin 16 to 21 (DIP)
CG0 for pin 15 and 22 (DIP)
CL0x
I/Ox
From
Adjacent
Pin
20V8–4
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage .................................................−0.5V to +7.0V
Output Current into Outputs (LOW)............................. 24 mA
DC Programming Voltage............................................. 12.5V
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
Commercial
0°C to +75°C
Industrial
Military[1]
40°C to +85°C
55°C to +125°C
Note:
1. TA is the “instant on” case temperature.
VCC
5V ±5%
5V ±10%
5V ±10%
3





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