Array Logic. PALCE16V8 Datasheet
PALCE16V8 COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
x Pin and function compatible with all 20-pin PAL® devices
x Electrically erasable CMOS technology provides reconﬁgurable logic and full testability
x High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
x Direct plug-in replacement for the PAL16R8 series
x Outputs programmable as registered or combinatorial in any combination
x Peripheral Component Interconnect (PCI) compliant
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
x 5-ns version utilizes a split leadframe for improved performance
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through ﬂoating-gate
cells in the AND logic array that can be erased electrically.
The ﬁxed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output conﬁguration
is determined by two global bits and one local bit controlling four multiplexers in each
Publication# 16493 Rev: F
Issue Date: September 2000
I1 – I8
Programmable AND Array
32 x 64
The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the
PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z
has zero standby power and an unused product term disable feature for reduced power
consumption. It has eight independently conﬁgurable macrocells (MC0-MC7). Each macrocell can
be conﬁgured as registered output, combinatorial output, combinatorial I/O or dedicated input.
The programming matrix implements a programmable AND logic array, which drives a ﬁxed OR
logic array. Buffers for device inputs have complementary outputs to provide user-
programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK)
and output enable (OE), respectively, for all ﬂip-ﬂops.
Unused input pins should be tied directly to VCC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are automatically conﬁgured from the user’s
design speciﬁcation. The design speciﬁcation is processed by development software to verify
the design and create a programming ﬁle (JEDEC). This ﬁle, once downloaded to a programmer,
conﬁgures the device according to the user’s desired function.
The user is given two design options with the PALCE16V8. First, it can be programmed as a
standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8.
The programmer will program the PALCE16V8 in the corresponding architecture. This allows
the user to use existing standard PAL device JEDEC ﬁles without making any changes to them.
2 PALCE16V8 and PALCE16V8Z Families
Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
1 1 Macrocell
1 1 OE 1 0
*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
Figure 1. PALCE16V8 Macrocell
Each macrocell can be conﬁgured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output conﬁguration, the output
buffer is enabled by the OE pin. In the combinatorial conﬁguration, the buffer is either controlled
by a product term or always enabled. In the dedicated input conﬁguration, it is always disabled.
With the exception of MC0 and MC7, a macrocell conﬁgured as a dedicated input derives the
input signal from an adjacent I/O. MC0 derives its input from pin 11 (OE) and MC7 from pin 1
The macrocell conﬁgurations are controlled by the conﬁguration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0x, in
conjunction with SG1, selects the conﬁguration of the macrocell, and SL1x sets the output as
either active low or active high for the individual macrocell.
The conﬁguration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In
MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
the adjacent pin for MC7 and OE the adjacent pin for MC0.
PALCE16V8 and PALCE16V8Z Families