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RGR1551 Dataheets PDF



Part Number RGR1551
Manufacturers Agilent(Hewlett-Packard)
Logo Agilent(Hewlett-Packard)
Description Fiber Optic Light to Logic Receiver with Clock Recovery
Datasheet RGR1551 DatasheetRGR1551 Datasheet (PDF)

Fiber Optic “Light to Logic” Receiver with Clock Recovery Preliminary Technical Data RGR1551 Features • Light to Logic 20-Pin DIP Receiver Offers ECL Compatibility • Long Reach, High Performance • Sensitivity: –36 dBm • Phase-Locked Loop (PLL) Timing Recovery Circuit • Meets SONET Jitter Tolerance Requirements (CCITT G.958) • Single +5 V Supply, Typically <700 mW • SONET OC3 and SDH STM1 Compatible • Multisourced Applications • Telecommunication Networks • SONET OC3 and SDH STM1 Compatible • .

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Fiber Optic “Light to Logic” Receiver with Clock Recovery Preliminary Technical Data RGR1551 Features • Light to Logic 20-Pin DIP Receiver Offers ECL Compatibility • Long Reach, High Performance • Sensitivity: –36 dBm • Phase-Locked Loop (PLL) Timing Recovery Circuit • Meets SONET Jitter Tolerance Requirements (CCITT G.958) • Single +5 V Supply, Typically <700 mW • SONET OC3 and SDH STM1 Compatible • Multisourced Applications • Telecommunication Networks • SONET OC3 and SDH STM1 Compatible • Local and Metropolitan Area Networks • ATM Single Mode Public Network • Military Communications and Control Systems • Digital Cable TV Networks to 1600 nm wavelength light wave information into an electrical signal at a data rate of 155 Mb/s. The receiver contains an InGaAs PIN photodiode, a high sensitivity, wide dynamic range transimpedance amplifier, capacitively coupled to a PLL based clock recovery circuit. The clock and data outputs are retimed complementary PECL. A complementary CMOS compatible low light alarm is also provided. Description The RGR1551 receiver provides optical signal conversion and processing. It converts 1200 nm Preliminary Product Disclaimer This preliminary data sheet is provided to assist you in the evaluation of engineering samples of the product which is under development and targeted for release during 1997. Until Hewlett-Packard releases this product for general sales, HP reserves the right to alter prices, specifications, features, capabilities, function, manufacturing release dates, and even general availability of the product at any time. 412 (5/97) Connection Diagram Top View FIBER PIGTAIL GND GND GND CLOCK CLOCK GND DATA GND DATA PD BIAS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC NC NC NC GND GND ALARM GND ALARM +5 V Pin Descriptions Pins 1, 2, 3, 6, 8, 13, 15, 16, GND: These pins should be connected to the circuit ground. Pins 4, 5, CLOCK, CLOCK: These pins provide complementary differential PECL CLOCK and CLOCK outputs. Pins 7, 9, DATA, DATA: These pins provide complementary differential PECL DATA and DATA outputs. The RGR1551 DATA output is noninverting, an optical pulse causes the DATA output to go to the PECL logic high state (+4 V nominal). Pin 10, PD Bias: This pin must be connected to any voltage between 0 V (GND) and –5 V. This provides the photodiode bias. The current drawn is directly proportional to the average received photocurrent. I = Responsivity x Mean Power. The Responsivity will be between 0.7 A/W and 1.0 A/W. Pin 11, +5 V: This pin should be connected to +5 V supply. The network shown below should be placed as close as possible to pin 11. Pins 12, 14, ALARM, ALARM: These pins provide complementary ALARM and ALARM outputs. This is the low light alarm. ALARM goes to a logic low (CMOS compatible) state when the optical power drops below the threshold level (insufficient optical power). The optical power must increase to a higher level than the level where the alarm went low before ALARM will return to a logic high. This difference is the alarm hysteresis. Pins 17, 18, 19, 20, NC: These pins are not connected and should be left open circuit on the application PCB. 1 µH +5 V PIN 11 10 µF 100 nF 100 nF 413 Functional Description Design The receiver contains an InGaAsP photodetector, transimpedance amplifier, and interface amplifier circuit, including a clock recovery and data retiming function. It is designed with a multimode fiber pigtail to allow maximum flexibility in connector options. The interface amplifier is ac coupled to the preamplifier circuit. Terminating the Outputs The data outputs of the RGR1551 are PECL compatible. Care should be taken to match termination impedances to the interconnect to minimize reflection effects. In order to balance the drive currents drawn from the module, all serial data outputs (DATA and DATA, CLOCK and CLOCK) should be terminated identically, even if only one output is used. This will lower the power supply noise generated by the receiver and improve performance at low optical input power levels. Power Supplies The RGR1551 will operate to specifications with a single +5 V power supply (Pin 10 grounded). The –5 V PIN bias is provided to maintain functional compatibility with second sources. Circuit Layout The RGR1551 uses very high bandwidth circuitry to achieve its high level of performance. Care must be taken to ensure stable operation. The use of ground planes and transmission line interconnects is required. The use of a standard evaluation board is highly recommended for those users who are not familiar with these techniques. Signal traces should conform to ECL design rules to prevent reflections and ringing from degrading performance. Useful guidelines are contained in ECL manufacturer design manuals. Manufacturing The fiber pigtail on the device requires normal fiber handling considerations. Care should be taken to avoid tight bends as well as excessive tension on the fiber pigtail. The allow.


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