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Array Logic. PALCE20V8 Datasheet |
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COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Pin and function compatible with all PAL® 20V8 devices
x Electrically erasable CMOS technology provides reconfigurable logic and full testability
x High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
x Direct plug-in replacement for a wide range of 24-pin PAL devices
x Programmable enable/disable control
x Outputs individually programmable as registered or combinatorial
x Peripheral Component Interconnect (PCI) compliant
x Preloadable output registers for testability
x Automatic register reset on power-up
x Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
x Programmable output polarity
x 5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the user’s design specification. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming file based on Boolean or state equations. Design software also verifies
the design and can provide test vectors for the finished device. Programming can be
accomplished on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
Publication# 16491 Rev: E
Amendment/0
Issue Date: November 1998
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The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
BLOCK DIAGRAM
I1 – I10
CLK/I0
10
Programmable AND Array
40 x 64
Input
Mux.
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
Input
Mux.
OE/I11 I12
I/O0
I/O1
I/O2
I/O3 I/O4
I/O5
I/O6 I/O7 I13
16491E
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells
(MC0-MC7). Each macrocell can be configured as a registered output, combinatorial output,
combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a fixed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to VCC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are automatically configured from the user’s
design specification, which can be in a number of formats. The design specification is processed
2 PALCE20V8 Family
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