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PAL Device. PALCE20V8 Datasheet |
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20V8
PALCE20V8
Flash Erasable,
Reprogrammable CMOS PAL Device
Features
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
— 65 mA max. military/industrial
(15, 25 ns)
• Standard version has low power
— 90 mA max. commercial
(15, 25 ns)
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• QSOP package available
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.
Logic Block Diagram (PDIP/CDIP/QSOP)
GND
12
I10
11
I9
10
I8 I7 I6
9 87
I5 I4
65
I3 I2 I1 CLK/I0
4 3 21
PROGRAMMABLE
AND ARRAY
(64 x 40)
8 8 8 88 8 8
8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
MUX
13 14
15
16
17
18
OE/I11
I12
I/O0
I/O1
I/O2
I/O3
PAL is a registered trademark of Advanced Micro Devices, Inc.
19
I/O4
20 21 22 23 24
I/O5 I/O6 I/O7 I13 VCC
20V8–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03026 Rev. **
Revised March 26, 1997
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PALCE20V8
Pin Configuration
DIP/QSOP
Top View
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I13
22 I/O7
21 I/O6
20 I/O5
19 I/O4
18 I/O3
17 I/O2
16 I/O1
15 I/O0
14 I12
13 OE/I11
20V8–2
PLCC/LCC
Top View
4 3 2 1 2827 26
I3 5
25 I/O6
I4 6
24 I/O5
I5 7
23 I/O4
NC 8
22 NC
I6 9
21 I/O3
I7 10
20 I/O2
I8 11 121314 1516 1718 19 I/O1
20V8–3
Selection Guide
Generic Part Number
tPD ns
Com’l/Ind Mil
PALCE20V8−5
5
PALCE20V8−7
7.5
PALCE20V8−10
10 10
PALCE20V8−15
15 15
PALCE20V8−25
25 25
PALCE20V8L−15
15 15
PALCE20V8L−25
25 25
Shaded area contains preliminary information.
tS ns
Com’l/Ind Mil
3
7
10 10
12 12
15 20
12 12
15 20
tCO ns
Com’l/Ind Mil
4
5
7 10
10 12
12 20
10 12
12 20
ICC mA
Com’l Mil/Ind
115
115
115 130
90 130
90 130
55 65
55 65
Functional Description (continued)
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, VCC, or
Ground to improve noise immunity and reduce ICC.
Document #: 38-03026 Rev. **
Page 2 of 14
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