PAL Device. PALCE22V10 Datasheet
PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25
PALCE22V10Z COM'L: -25
PALCE22V10 and PALCE22V10Z
24-Pin EE CMOS (Zero Power) Versatile PAL Device
x As fast as 5-ns propagation delay and 142.8 MHz fMAX (external)
x Low-power EE CMOS
x 10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
x Varied product term distribution allows up to 16 product terms per output for complex
x Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)
x Global asynchronous reset and synchronous preset for initialization
x Power-up reset for initialization and register preload for testability
x Extensive third-party software and programmer support
x 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC
x 5-ns and 7.5-ns versions utilize split leadframes for improved performance
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and
ﬂip-ﬂops at a reduced chip count.
The PALCE22V10Z is an advanced PAL® device built with zero-power, high-speed, electrically-
erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-
power CMOS SSI/MSI gates and ﬂip-ﬂops at a reduced chip count.
The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby
current, the PALCE22V10Z allows battery-powered operation for an extended period.
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The
PAL device is a programmable AND array driving a ﬁxed OR array. The AND array is programmed
to create custom product terms, while the OR array sums selected terms at the outputs.
The product terms are connected to the ﬁxed OR array with a varied distribution from 8 to16 across
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each
macrocell can be programmed as registered or combinatorial, and active-high or active low. The
output conﬁguration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 16564 Rev: E
Issue Date: November 1998
I1 - I11
(44 x 132)
12 14 16 16
14 12 10
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9
The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming
EE cells to conﬁgure AND and OR gates within the device, according to the desired logic function.
Complex interconnections between gates, which previously required time-consuming layout, are
lifted from the PC board and placed on silicon, where they can be easily modiﬁed during
prototyping or production.
The PALCE22V10Z is the zero-power version of the PALCE22V10. It has all the architectural features
of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product
Product terms with all connections opened assume the logical HIGH state; product terms
connected to both true and complement of any single input assume the logical LOW state.
The PALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four
potential output conﬁgurations registered output or combinatorial I/O, active high or active low
(see Figure 1). The conﬁguration choice is made according to the user’s design speciﬁcation and
corresponding programming of the conﬁguration bits S0 - S1. Multiplexer controls are connected
to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing
the bit disconnects the control line from GND and it is driven to a high level, selecting the “1” path.
The device is produced with an EE cell link at each input to the AND gate array, and connections
may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-
implemented programming algorithm, these products can be rapidly programmed to any
2 PALCE22V10 and PALCE22V10Z Families
Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to VCC or GND.
0 0 Registered/Active Low
0 1 Registered/Active High
1 0 Combinatorial/Active Low
1 1 Combinatorial/Active High
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
Registered Output Conﬁguration
Each macrocell of the PALCE22V10 includes a D-type ﬂip-ﬂop for data storage and
synchronization. The ﬂip-ﬂop is loaded on the LOW-to-HIGH transition of the clock input. In the
registered conﬁguration (S1 = 0), the array feedback is from Q of the ﬂip-ﬂop.
Combinatorial I/O Conﬁguration
Any macrocell can be conﬁgured as combinatorial by selecting the multiplexer path that bypasses
the ﬂip-ﬂop (S1 = 1). In the combinatorial conﬁguration, the feedback is from the pin.
PALCE22V10 and PALCE22V10Z Families