Document
PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25 PALCE22V10Z COM'L: -25 IND: -15/25
PALCE22V10 and PALCE22V10Z Families
24-Pin EE CMOS (Zero Power) Versatile PAL Device DISTINCTIVE CHARACTERISTICS
x As fast as 5-ns propagation delay and 142.8 MHz fMAX (external) x Low-power EE CMOS x 10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
x Varied product term distribution allows up to 16 product terms per output for complex x x x x x x
functions Peripheral Component Interconnect (PCI) compliant (-5/-7/-10) Global asynchronous reset and synchronous preset for initialization Power-up reset for initialization and register preload for testability Extensive third-party software and programmer support 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC 5-ns and 7.5-ns versions utilize split leadframes for improved performance
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z is an advanced PAL® device built with zero-power, high-speed, electricallyerasable CMOS technology. It provides user-programmable logic for replacing conventional zeropower CMOS SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby current, the PALCE22V10Z allows battery-powered operation for an extended period. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active-high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 16564 Amendment/0
Rev: E Issue Date: November 1998
BLOCK DIAGRAM
CLK/I0 1 11 I1 - I11
PROGRAMMABLE AND ARRAY (44 x 132)
8 10 12 14 16 16 14 12 10 8
RESET
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL PRESET
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
FUNCTIONAL DESCRIPTION
The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming EE cells to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified .