Array Logic. PALCE29MA16H-25 Datasheet

PALCE29MA16H-25 Logic. Datasheet pdf. Equivalent

PALCE29MA16H-25 Datasheet
Recommendation PALCE29MA16H-25 Datasheet
Part PALCE29MA16H-25
Description 24-Pin EE CMOS Programmable Array Logic
Feature PALCE29MA16H-25; FINAL COM’L: H-25 PALCE29MA16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERIST.
Manufacture Advanced Micro Devices
Datasheet
Download PALCE29MA16H-25 Datasheet





Advanced Micro Devices PALCE29MA16H-25
FINAL
COM’L: H-25
PALCE29MA16H-25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s High-performance semicustom logic
replacement; Electrically Erasable (EE)
technology allows reprogrammability
s 16 bidirectional user-programmable I/O logic
macrocells for Combinatorial/Registered/
Latched operation
s Output Enable controlled by a pin or product
terms
s Varied product term distribution for increased
design flexibility
s Programmable clock selection with common
pin clock/latch enable (LE) or individual
product term clock/LE with LOW/HIGH clock/
LE polarity
GENERAL DESCRIPTION
The PALCE29MA16 is a high-speed, EE CMOS Pro-
grammable Array Logic (PAL) device designed for gen-
eral logic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high
BLOCK DIAGRAM
s Register/Latch Preload permits full logic
verification
s High speed (tPD = 25 ns, fMAX = 33 MHz and fMAX
internal = 50 MHz)
s Full-function AC and DC testing at the factory
for high programming and functional yields
and high reliability
s 24-pin 300 mil SKINNYDIP and 28-pin plastic
leaded chip carrier packages
s Extensive third-party software and programmer
support through FusionPLD partners
programming yield, fast programming, and excellent
reliability. PAL devices combine the flexibility of custom
logic with the off-the-shelf availability of standard
products, providing major advantages over other
CLK/LE
I/OF7
I/OF6
I/O7
I/O6
I/O 5
I/O 4
I/OF5
I/OF4
I/O
Logic
Macrocell
4
4
I/O
Logic
Macrocell
4
4
I/O
Logic
Macrocell
4
8
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
4
12
4
12
4
8
4
4
4
4
Programmable
AND Array
58x178
4
4
4
4
8
4
12
4
12
4
8
4
4
4
4
4
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
4
I 0 -I3 I/OE
I/OF0
I/OF1
I/O0
I/O1
I/O2
I/O3
I/OF2
I/OF3
08811G-1
Publication# 08811 Rev. G Amendment /0
Issue Date: June 1993
2-349



Advanced Micro Devices PALCE29MA16H-25
AMD
GENERAL DESCRIPTION (continued)
semicustom solutions such as gate arrays and standard
cells, including reduced development time and low up-
front development cost.
The PALCE29MA16 uses the familiar sum-of-products
(AND-OR) structure, allowing users to customize logic
functions by programming the device for specific appli-
cations. It provides up to 29 array inputs and 16 outputs.
It incorporates AMD’s unique input/output logic macro-
cell which provides flexible input/output structure and
polarity, flexible feedback selection, multiple Output En-
able choices, and a programmable clocking scheme.
The macrocells can be individually programmed as
combinatorial, registered, or latched with active-HIGH
or active-LOW polarity. The flexibility of the logic macro-
cells permits the system designer to tailor the device to
particular application requirements.
Increased logic power has been built into the
PALCE29MA16 by providing a varied number of logic
CONNECTION DIAGRAMS
Top View
SKINNYDIP
product terms per output. Of the 16 outputs, 8 outputs
have 4 product terms each, 4 outputs have 8 product
terms each, and the other 4 outputs have 12 product
terms each. This varied product-term distribution allows
complex functions to be implemented in a single PAL
device. Each output can be dynamically controlled by a
common Output Enable pin or Output Enable product
term. Each output can also be permanently enabled or
disabled.
System operation has been enhanced by the addition of
common asynchronous-Preset and Reset product
terms and a power-up Reset feature. The
PALCE29MA16 also incorporates Preload and Obser-
vability functions which permit full logic verification of
the design.
The PALCE29MA16 is offered in the space-saving
300-mil SKINNYDIP package as well as the plastic
leaded chip carrier package.
PLCC
CLK/LE
I0
I/OF0
I/OF1
I/O0
I/O1
I/O2
I/O3
I/OF2
I/OF3
I/OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I3
22 I/OF7
21 I/OF6
20 I/O7
19 I/O6
18 I/O5
17 I/O4
16 I/OF5
15 I/OF4
14 I2
13 I1
Note:
Pin 1 is marked for orientation.
08811G-2
I/OF1
I/O0
I/O1
NC
I/O2
I/O3
I/OF2
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/OF6
I/O7
I/O6
NC
I/O5
I/O4
I/OF5
08811G-3
PIN DESIGNATIONS
CLK/LE = Clock or Latch Enable
GND = Ground
I = Input
I/O = Input/Output
I/OF = Input/Output with Dual Feedback
VCC = Supply Voltage
NC = No Connection
2-350
PALCE29MA16H-25



Advanced Micro Devices PALCE29MA16H-25
AMD
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of these elements:
PAL CE 29 MA 16 H -25 P C /4
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF ARRAY INPUTS
OUTPUT TYPE
MA = Advanced Asynchronous Macrocell
NUMBER OF FLIP-FLOPS
POWER
H = Half Power (100 mA)
SPEED
-25 = 25 ns
OPTIONAL PROCESSING
Blank = Standard Processing
PROGRAMMING REVISION
/4 = First Revision
(Requires current
programming Algorithm)
TEMPERATURE RANGE
C = Commercial (0°C to +75°C)
PACKAGE TYPE
P = 24-Pin Plastic SKINNYDIP
(PD3024)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
Valid Combinations
PALCE29MA16H-25 PC, JC
/4
Valid Combinations
Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
PALCE29MA16H-25 (Com’l)
2-351





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