Array Logic. PALLV16V8-10SC Datasheet
PALLV16V8-10 and PALLV16V8Z-20
Low Voltage, Zero Power 20-Pin EE CMOS
Universal Programmable Array Logic
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = +3.0 V to +3.6 V
x Pin and function compatible with all 20-pin PAL® devices
x Electrically-erasable CMOS technology provides reconﬁgurable logic and full testability
x Direct plug-in replacement for the PAL16R8 series
x Designed to interface with both 3.3-V and 5-V logic
x Outputs programmable as registered or combinatorial in any combination
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable
CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells
provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the
exception of the PAL16C1.
The PALLV16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALLV16V8Z allows battery powered operation for an extended period.
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic can
always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through ﬂoating-gate cells
in the AND logic array that can be erased electrically.
The ﬁxed OR array allows up to eight data product terms per output for logic functions. The sum
of these products feeds the output macrocell. Each macrocell can be programmed as registered or
combinatorial with an active-high or active-low output. The output conﬁguration is determined by
two global bits and one local bit controlling four multiplexers in each macrocell.
Publication# 17713 Rev: E
Issue Date: November 1998
I1 - I8
Programmable AND Array
32 x 64
The PALLV16V8 is a low-voltage, EE CMOS version of the PALCE16V8.
The PALLV16V8Z is a low-voltage, EE CMOS version of the PALCE16V8. In addition, the
PALLV16V8Z has zero standby power and an unused product term disable feature for reduced
The PALLV16V8 is a universal PAL device. It has eight independently conﬁgurable macrocells
(MC0-MC7). Each macrocell can be conﬁgured as registered output, combinatorial output,
combinatorial I/O or dedicated input. The programming matrix implements a programmable AND
logic array, which drives a ﬁxed OR logic array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array
inputs or as clock (CLK) and output enable (OE), respectively, for all ﬂip-ﬂops.
Unused input pins should be tied directly to VCC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALLV16V8 are automatically conﬁgured from the user’s
design speciﬁcation. The design speciﬁcation is processed by development software to verify the
design and create a programming ﬁle. This ﬁle, once downloaded to a programmer, conﬁgures the
device according to the user’s desired function.
2 PALLV16V8-10 and PALLV16V8Z-20 Families