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PAL Device. PALLV22V10 Datasheet |
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PALLV22V10 COM'L: -7/10/15
PALLV22V10Z
IND: -15
IND: -25
PALLV22V10 and PALLV22V10Z Families
Low-Voltage (Zero Power) 24-Pin EE CMOS
Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = + 3.0 V to 3.6 V
x Commercial and industrial operating temperature range
x 7.5-ns tPD
x Electrically-erasable technology provides reconfigurable logic and full testability
x 10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
x Varied product term distribution allows up to 16 product terms per output for complex
functions
x Global asynchronous reset and synchronous preset for initialization
x Power-up reset for initialization and register preload for testability
x Extensive third-party software and programmer support
x 24-pin SKINNY DIP and 28-pin PLCC packages save space
GENERAL DESCRIPTION
The PALLV22V10 is an advanced PAL® device built with low-voltage, high-speed, electrically-
erasable CMOS technology.
The PALLV22V10Z provides low voltage and zero standby power. At 30 µA maximum standby
current, the PALLV22V10Z allows battery powered operation for an extended period.
The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of
products. The PAL device is a programmable AND array driving a fixed OR array. The AND array
is programmed to create custom product terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to 16
across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell.
Each macrocell can be programmed as registered or combinatorial, and active high or active low.
The output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 18956 Rev: F
Amendment/0
Issue Date: September 2000
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BLOCK DIAGRAM
CLK/I0
1
I1 - I11
11
PROGRAMMABLE
AND ARRAY
(44 x 132)
8 10
12 14 16 16
14 12 10
8
RESET
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
PRESET
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9
18956D-001
FUNCTIONAL DESCRIPTION
The PALLV22V10 is the low-voltage version of the PALCE22V10. It has all the architectural features
of the PALCE22V10.
The PALLV2210Z is the low-voltage, zero-power version of the PALCE22V10. It has all the
architectural features of the PALCE22V10. In addition, the PALLV22V10Z has zero standby power
and an unused product term disable feature.
The PALLV22V10 allows the systems engineer to implement a design on-chip by programming EE
cells to configure AND and OR gates within the device, according to the desired logic function.
Complex interconnections between gates, which previously required time-consuming layout, are
lifted from the PC board and placed on silicon, where they can be easily modified during
prototyping or production.
Product terms with all connections opened assume the logical HIGH state; product terms
connected to both true and complement of any single input assume the logical LOW state.
The PALLV22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four
potential output configurations; registered output or combinatorial I/O, active high or active low
(see Figure 2). The configuration choice is made according to the user’s design specification and
corresponding programming of the configuration bits S0 - S1. Multiplexer controls are connected
to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing
the bit disconnects the control line from GND and it floats to VCC (1), selecting the “1” path.
The device is produced with a EE cell link at each input to the AND gate array, and connections
may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-
implemented programming algorithm, these products can be rapidly programmed to any
customized pattern.
2 PALLV22V10 and PALLV22V10Z Families
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Variable Input/Output Pin Ratio
The PALLV22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to VCC or GND.
Registered Output Configuration
Each macrocell of the PALLV22V10 includes a D-type flip-flop for data storage and synchronization.
The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered
configuration (S1 = 0), the array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses
the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin.
AR
DQ
CLK Q
SP
0
1
10
11
00
01
S1
S0
I/On
S1 S0 Output Configuration
0 0 Registered/Active Low
0 1 Registered/Active High
1 0 Combinatorial/Active Low
1 1 Combinatorial/Active High
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
18956C-004
PALLV22V10 and PALLV22V10Z Families
3
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