QL4016-4PF100C

QL4016 QuickRAM Data Sheet 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density 16,000 Usable PLD Gates with 118 I/Os 300 MHz 16-bit Counters, 400 MHz Advanced I/O Capabilities Interfaces with both 3.3 V and 5.0 V devices PCI compliant with 3.3 V and 5.0 V busses Datapaths, 160+ MHz FIFOs 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes for -1/-2/-3/-4 speed grades Full JTAG boundary scan I/O Cells with individually controlled Registered Input Path and Output Enables High Speed Embedded SRAM 10 dual-port RAM modules, organized in user-configurable 1,152 bit blocks 5 ns access times, each port independently accessible Fast and efficient for FIFO, RAM, and ROM functions 10 RAM Blocks 320 High Speed Logic Cells Easy to Use / Fast Development Cycles 100% routable with 100% utilization and Interface complete pin-out stability Variable-grain logic cells provide high performance and 100% utilization Comprehensive design tools include high quality Verilog/VHDL synthesis Figure 1: QuickRAM Block Diagram © 2002 QuickLogic Corporation www.quicklogic.com 1 QL4016 QuickRAM Data Sheet Rev I Architecture Overview The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. The QL4016 is a 16,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs...