DatasheetsPDF.com

QS5LV91955J Dataheets PDF



Part Number QS5LV91955J
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3V LOW SKEW CMOS PLL CLOCK DRIVER
Datasheet QS5LV91955J DatasheetQS5LV91955J Datasheet (PDF)

QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: DESCRIPTION: QS5LV919 • • • • • • • • • • • • • 3.3V operation JEDEC compatible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0–Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC networ.

  QS5LV91955J   QS5LV91955J



Document
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: DESCRIPTION: QS5LV919 • • • • • • • • • • • • • 3.3V operation JEDEC compatible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0–Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to MC88LV915, IDT74FCT388915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q 0-Q 4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q 0-Q 4, and Q/2 outputs. The QS5LV919 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5LV919 is designed for use in high-performance workstations, multiboard computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM REF_SEL LO CK SYNC 0 SYNC 1 O E/RST 0 0 1 PH A SE DETECTO R LOO P FILTER 1 PE FEEDBACK PLL_EN FREQ _SEL VCO 1 /2 0 R D R D R D R D R D R D R D Q Q Q Q Q Q Q Q Q /2 Q5 Q4 Q3 Q2 Q1 Q0 2xQ INDUSTRIAL TEMPERATURE RANGE 1 c 2001 Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. JULY 2001 DSC-5820/3 QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION OE/RST GND Q5 VDD OE/RST FEEDBACK REF_SEL SYNC0 AVDD PE AGND SYNC1 FREQ_SEL GND Q0 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD 2xQ Q/2 GND Q3 VDD Q2 GND LOCK PLL_EN GND Q1 VDD AGND SYNC1 10 11 FEEDBACK REF_SEL SYNC0 AVDD PE 5 6 7 8 9 4 3 2 1 28 27 26 25 24 23 22 21 20 19 Q/2 GND Q3 VDD Q2 GND LOCK 12 FREQ_SEL 13 GND 14 Q0 15 VDD 16 Q1 17 GND 18 PLL_EN QSOP TOP VIEW PLCC TOP VIEW ABSOLUTE MAXIMUM RATINGS (1) Symbol Rating DC Input Voltage VIN Maximum Power TSTG QSOP Dissipation (TA = 85°C) PLCC Storage Temperature Range Max. –0.5 to +7 –0.5 to +5.5 655 770 –65 to +150 Unit V V mW mW °C VDD, AVDD Supply Vol.


QS5LV919160Q QS5LV91955J QS5LV91955Q


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)