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PC87311A Dataheets PDF



Part Number PC87311A
Manufacturers National Semiconductor
Logo National Semiconductor
Description Floppy Disk Controller
Datasheet PC87311A DatasheetPC87311A Datasheet (PDF)

PC87311A PC87312 (SuperI O II III) Floppy Disk Controller with Dual UARTs Parallel Port and IDE Interface October 1993 PC87311A PC87312 (SuperI O TM II III) Floppy Disk Controller with Dual UARTs Parallel Port and IDE Interface General Description The PC87311A 12 incorporates a floppy disk controller (FDC) two full function UARTs a bidirectional parallel port and IDE interface control logic in one chip The PC87311A includes standard AT XT address decoding for on-chip functions and a Configurat.

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PC87311A PC87312 (SuperI O II III) Floppy Disk Controller with Dual UARTs Parallel Port and IDE Interface October 1993 PC87311A PC87312 (SuperI O TM II III) Floppy Disk Controller with Dual UARTs Parallel Port and IDE Interface General Description The PC87311A 12 incorporates a floppy disk controller (FDC) two full function UARTs a bidirectional parallel port and IDE interface control logic in one chip The PC87311A includes standard AT XT address decoding for on-chip functions and a Configuration Register offering a single chip solution to the most commonly used IBM PC PC-XT and PC-AT peripherals The PC87312 includes standard AT address decoding for on-chip functions and a Configuration Register set offering a single chip solution to the most commonly used ISA EISA and Micro Channel peripherals The on-chip FDC is software compatible to the PC8477 which contains a superset of the DP8473 and NEC mPD765 and the N82077 floppy disk controller functions The onchip analog data separator requires no external components and supports the 4 Mb drive format as well as the other standard floppy drives used with 5 25 and 3 5 media In the PC87311A the UARTs are equivalent to two INS8250N-Bs or NS16450s The bidirectional parallel port maintains complete compatibility with the IBM PC XT and AT In the PC87312 the UARTs are equivalent to two NS16450s or PC16550s The bidirectional parallel port maintains complete compatibility with the ISA EISA and Micro Channel parallel ports The IDE control logic provides a complete IDE interface except for the signal buffers The Configuration Registers consist of three byte-wide registers An Index and a Data Register which can be relocated within the ISA I O address space access the Configuration Registers Features Y Y Y Y Y Y Y 100% compatible with IBM PC XT and AT architectures (PC87311A) or ISA EISA and Micro Channel architectures (PC87312) FDC Software compatible with the DP8473 the 765A and the N82077 16-byte FIFO (default disabled) Burst and Non-Burst modes Perpendicular Recording drive support High performance internal analog data separator (no external filter components required) Low power CMOS with power down mode UARTs Software compatible with the INS8250N-B and the NS16450 (PC87311A) or PC16550A and PC16450 (PC87312) Parallel Port Bidirectional under either software or hardware control Compatible with all IBM PC XT and AT architectures (PC87311A) or all ISA EISA and Micro Channel architectures (PC87312) Back Voltage protection circuit against damage caused when printer is powered up IDE Control Logic Provides a complete IDE interface except for optional buffers Address Decoder Provides selection of all primary and secondary ISA addresses including COM 1 – 4 100-pin PQFP package The PC87311A and PC87312 are pin compatible Block Diagram TL F 11362 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation SuperI OTM is a trademark of National Semiconductor Corporation IBM PC PC-AT PC-XT and PS 2 are registered trademarks of International Business Machines Corporation C1995 National Semiconductor Corporation TL F 11362 RRD-B30M75 Printed in U S A Table of Contents 1 0 PIN DESCRIPTION 2 0 CONFIGURATION REGISTERS 2 1 Overview 2 2 Software Configuration 2 3 Hardware Configuration 2 4 Index and Data Registers 2 5 Base Configuration Registers 2 5 1 Function Enable Register (FER) 2 5 2 Function Address Register (FAR) 2 5 3 Power and Test Register (PTR) 2 6 Power Down Options 2 7 Power Up Procedure and Considerations 2 7 1 Crystal Stabilization 2 7 2 UART Power-Up 2 7 3 FDC Power-Up 3 0 FDC REGISTER DESCRIPTION 3 1 Status Register A (SRA) 3 1 1 SRA PS 2 Mode 3 1 2 SRA Model 30 Mode 3 2 Status Register B (SRB) 3 2 1 SRB PS 2 Mode 3 2 2 SRB Model 30 Mode 3 3 Digital Output Register (DOR) 3 4 Tape Drive Register (TDR) 3 5 Main Status Register (MSR) 3 6 Data Rate Select Register (DSR) 3 7 Data Register (FIFO) 3 8 Digital Input Register (DIR) 3 8 1 DIR PC-AT Mode 3 8 2 DIR PS 2 Mode 3 8 3 DIR Model 30 Mode 3 9 Configuration Control Register (CCR) 3 9 1 CCR PC-AT and PS 2 Modes 3 9 2 CCR Model 30 Mode 3 10 Result Phase Status Registers 3 10 1 Status Register 0 (ST0) 3 10 2 Status Register 1 (ST1) 3 10 3 Status Register 2 (ST2) 3 10 4 Status Register 3 (ST3) 4 0 FDC COMMAND SET DESCRIPTION 4 1 Command Set Summary 4 2 Command Description 4 2 1 Configure Command 4 2 2 Dumpreg Command 4 2 3 Format Track Command 4 2 4 Invalid Command 4 2 5 Lock Command 4 2 6 Mode Command 4 2 7 NSC Command 4 2 8 Perpendicular Mode Command 4 2 9 Read Data Command 6 12 12 12 12 14 14 14 16 16 16 17 17 17 17 17 18 19 19 19 19 19 20 20 20 21 22 22 22 22 22 23 23 23 23 23 23 24 24 24 24 28 28 29 29 32 32 32 33 33 34 2 4 2 10 Read Deleted Data Command 4 2 11 Read ID Command 4 2 12 Read A Track Command 4 2 13 Recalibrate Command 4 2 14 Relative Seek Command 4 2 15 Scan Commands 4 2 16 Seek Command 4 2 17 Sense Drive Status Command 4 2 18 Sense Interrupt Command 4 2 19 Set Track Command 4 2 2.


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