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PC87372 Dataheets PDF



Part Number PC87372
Manufacturers National Semiconductor
Logo National Semiconductor
Description LPC SuperI/O with Glue Functions
Datasheet PC87372 DatasheetPC87372 Datasheet (PDF)

PC87372 LPC SuperI/O with Glue Functions October 2002 Revision 1.2 PC87372 LPC SuperI/O with Glue Functions General Description The National PC87372 Advanced I/O product is a member of the PC8737x SuperI/O family. All PC8737x devices are highly integrated and are pin and software compatible, thus providing drop-in interchangeability and enabling a variety of assembly options using only a single motherboard and BIOS. PC87372 integration allows for a smaller system board size and saves on total .

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PC87372 LPC SuperI/O with Glue Functions October 2002 Revision 1.2 PC87372 LPC SuperI/O with Glue Functions General Description The National PC87372 Advanced I/O product is a member of the PC8737x SuperI/O family. All PC8737x devices are highly integrated and are pin and software compatible, thus providing drop-in interchangeability and enabling a variety of assembly options using only a single motherboard and BIOS. PC87372 integration allows for a smaller system board size and saves on total system cost. The PC87372 includes legacy SuperI/O functions, system glue functions, fan monitoring and control, commonly used functions such as GPIO, and ACPI-compliant Power Management support. The PC87372 integrates miscellaneous analog and digital system glue functions to reduce the number of discrete components required. The host communicates with the functions integrated in the PC87372 device through an LPC Bus Interface. The PC87372 Legacy functions are: a serial port (UART), a fully compliant IEEE 1284 Parallel Port, a Floppy Disk Controller (FDC) and a Keyboard/Mouse Controller (KBC). The Fan Speed Monitor (FSM) module allows the system to monitor two fans. Semiconductor® The PC87372 extended wake-up support complements the ACPI controller in the chipset. The System Wake-Up Control (SWC) module, powered by VSB3, supports a flexible wakeup mechanism. There are 13 General-Purpose Input/Output (GPIO) ports; these allow system control and wake-up on system events. Outstanding Features s Legacy modules: Parallel Port, Floppy Disk Controller (FDC), Serial Port and a Keyboard and Mouse Controller (KBC) Glue functions to complement the South Bridge functionality Fan Speed monitoring of two fans VSB3-powered Power Management with 20 wake-up sources Controls three LED indicators 13 GPIO ports with a variety of wake-up options LPC interface, based on Intel’s LPC Interface Specification Revision 1.0, September 29th, 1997 PC01 Revision 1.0 and Advanced Configuration and Power Interface (ACPI) Specification Revision 2.0 compliant 128-pin PQFP package s s s s s s s s Block Diagram 14.31818 MHz Serial Interface Parallel Port Interface IEEE 1284 Parallel Port Floppy Drive Interface Floppy Disk Controller Keyboard Mouse Interface Interface Keyboard & Mouse Controller LPC Serial Interface IRQ LPC Bus Interface Clock Generator Serial Port VDD3 48 MHz Internal Bus VSB3 Fan Speed Monitor Tachometer Inputs Glue Functions Miscellaneous I/O System Wake-Up Control Wake-Up Events GPIO Ports PnP Configuration Registers PME I/O Ports 32.768 KHz National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders. © 2002 National Semiconductor Corporation www.national.com PC87372 Features Bus Interface s LPC Bus Interface — Based on Intel’s LPC Interface Specification Revision 1.0, September 29, 1997 — Synchronous cycles using up to 33 MHz bus clock — 8-bit I/O read and write cycles — Up to four 8-bit DMA channels — Serial IRQ (SERIRQ) — Reset input (PCI_RESET) — Optional power-down support (LPCPD) Configuration Control — PnP Configuration Register structure — Compliant with PC01 Specification Revision 1.0, 1999-2000 — Base Address strap (BADDR) to setup the address of the Index-Data register pair (defaults to 2Eh/2Fh) — Flexible resource allocation for all logical devices: ❏ Relocatable base address ❏ ❏ — Perpendicular recording drive support for 2.88 MBytes — Burst (16-byte FIFO) and Non-Burst modes — Full support for IBM Tape Drive Register (TDR) implementation of AT and PS/2 drive types — High-performance digital separator — Supports fast tape drives (2 Mbps) and standard tape drives (1 Mbps, 500 Kbps and 250 Kbps) s s Keyboard and Mouse Controller (KBC) — 8-bit microcontroller, software compatible with 8042AH and PC87911 — Standard interface (60h, 64h, IRQ1 and IRQ12) — Supports two external swapable PS/2 interfaces for keyboard and mouse — Programmable, dedicated quasi-bidirectional I/O lines (GA20/P21, KBRST/P20) General-Purpose Modules s 15 IRQ routing options to serial IRQ Up to four optional 8-bit DMA channels General-Purpose I/O (GPIO) Ports — 13 GPIO ports powered by VSB3 — Each pin individually configured as input or output — Programmable features for each output pin: ❏ Drive type (open-drain, push-pull or TRI-STATE) ❏ — Configurable feature sets: ❏ Software selectable ❏ VSB3-powered pin multiplexing Legacy Modules s TRI-STATE on detection of falling VDD3 for VSB3-powered pins driving VDD-supplied devices Serial Port — Software compatible with the NS16550A and the NS16450 — Supports shadow register for write-only bit monitoring — Data rates up to 1.5 Mbaud IEEE 1284-compliant Parallel Port — ECP, with Level 2 (14 mA sink and source output buffers) — Software or hardware control — Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9 — Supports EPP as.


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