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PC87417 Dataheets PDF



Part Number PC87417
Manufacturers National Semiconductor
Logo National Semiconductor
Description LPC ServerI/O for Servers and Workstations
Datasheet PC87417 DatasheetPC87417 Datasheet (PDF)

PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations July 2003 Revision 1.2 PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations General Description The National Semiconductor PC8741x family of LPC ServerI/O devices (“PC8741x”) comprises highly integrated Advanced I/O products. The PC8741x is targeted for a wide range of servers and workstations that use the Low Pin Count (LPC) bus for the host interface and the serial ACCESS.bus or SMBus® for .

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PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations July 2003 Revision 1.2 PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations General Description The National Semiconductor PC8741x family of LPC ServerI/O devices (“PC8741x”) comprises highly integrated Advanced I/O products. The PC8741x is targeted for a wide range of servers and workstations that use the Low Pin Count (LPC) bus for the host interface and the serial ACCESS.bus or SMBus® for the embedded controller interface. The PC8741x features an X-Bus extension for read and write operations over the X-Bus for both LPC and ACCESS.bus cycles. Boot Flash and I/O devices can be accessed over this X-Bus. Embedded controllers can access the PC8741x and its X-Bus via the ACCESS.bus or SMBus serial interface when VSB exists, regardless of the LPC bus state. Some of the PC8741x logical devices can be disabled, or their pins can be floated, under control of the VSB-powered serial bus. The PC8741x provides a VSB-powered high-frequency clock for on-chip peripherals and for other VSB-powered platform components. The PC8741x’s extended wake-up support complements the chipset’s ACPI controller and the platform embedded controllers. The PC8741x can monitor the Power and Sleep buttons and control the power supply of simple platforms that lack an embedded controller. The System Wake-Up Control (SWC) module is powered by VSB and VBAT power supplies. It sup® ports flexible wake-up and power-off request mechanisms in any sleep state. It features Main and Standby power-on elapsed-time counters. The PC8741x also incorporates a Floppy Disk Controller (FDC), two serial ports (UARTs), a Keyboard and Mouse Controller (KBC), a Real-Time Clock (RTC), a fully compliant IEEE 1284 Parallel Port, General-Purpose Input/Output (GPIO) for a total of 51 ports and an Interrupt Serializer for Parallel IRQs. Outstanding Features s s s s s s s s s LPC Interface, based on Intel’s LPC Interface Specification, Revision 1.0, September 29th, 1997 VSB-powered access to modules through ACCESS.bus or SMBus (PC87413 and PC87417) X-Bus Extension for memory and I/O (PC87416 and PC87417) PC01 Revision 0.5 and ACPI Revision 1.0b compliant ServerI/O modules: Parallel Port, FDC, two Serial Ports (UARTs) and a Keyboard and Mouse Controller (KBC) Y2K-compliant RTC with 242 bytes of RAM 51 GPIO ports with a variety of wake-up events Extremely low current consumption in Battery Backup mode 128-pin PQFP package Block Diagram PC87417 (See page 5 for other PC8741x diagrams.) Serial Serial Interface Interface ServerI/O Clock VDD Serial Port 1 Serial Port 2 Parallel Port Interface IEEE 1284 Parallel Port Floppy Drive Interface Floppy Disk Controller LPC Serial Keyboard Mouse Interface Interface Interface IRQ Keyboard & Mouse Controller LPC Bus Interface Device Configuration VBAT VSB Power System On Wake-Up Control Timers RTC Internal Clocks Clock Generator GPIO Ports X-Bus Extension ACCESS.bus Interface Wake-Up Power SCI & Events Control SMI Low-F High-F 32.768 KHz Clock Clock X-Bus XIRQ I/O Ports Interface Clock Serial Data National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders. © 2003 National Semiconductor Corporation www.national.com PC8741x Features Bus Interfaces s s LPC Bus Interface — Based on Intel’s LPC Interface Specification Revision 1.0, September 29, 1997 — Synchronous cycles using up to 33 MHz bus clock — 8-bit I/O and Memory read and write cycles — Up to four 8-bit DMA channels — Serial IRQ — Supports bootable memory — Reset input — CLKRUN support — FWH Transaction support ACCESS.bus (ACB) Interface (PC87413 and PC87417) — Enables a system controller to access the internal functions and the X-Bus extension — Supports slave operation compatible with: ❏ Intel SMBus ❏ Configuration Control (via LPC bus) — Compliant with PC01 Specification Revision 0.5, November 2, 1999 — Plug and Play (PnP) Configuration register structure — Base Address strap to setup the address of the Index-Data register pair — Flexible resource allocation for all logical devices: ❏ Relocatable base address ❏ ❏ 15 IRQ routing options to serial IRQ Up to four optional 8-bit DMA channels — ACCESS.bus control over pin multiplexing, module disable and output TRI-STATE for all Legacy modules (PC87413 and PC87417) s Legacy Modules s ACCESS.bus s Serial Ports 1 and 2 — Software compatible with the 16550A and the 16450 — Supports shadow register for write-only bit monitoring — UART data rates up to 1.5 Mbaud IEEE 1284-compliant Parallel Port — ECP, with Level 2 (14 mA sink and source output buffers) — Software or hardware control — Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9 — Supports EPP as mode 4 of the Extended Control Register (ECR) — Selection of internal pull-up or pull-down resistor for Paper End (PE.


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