DatasheetsPDF.com

IDT7M1024 Dataheets PDF



Part Number IDT7M1024
Manufacturers Integrated Device
Logo Integrated Device
Description 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
Datasheet IDT7M1024 DatasheetIDT7M1024 Datasheet (PDF)

4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE Integrated Device Technology, Inc. IDT7M1024 FEATURES: • High-density 4K x 36 Synchronous Dual-Port SRAM module • Architecture based on Dual-Port RAM cells — Allows full simultaneous access from both ports • Synchronous operation — 4ns set-up to clock, 1ns hold on all control, data, and address inputs — Data input, address, and control registers — Fast 20ns clock to data out — Self-timed write allows fast write cycle • Clock enable feature.

  IDT7M1024   IDT7M1024



Document
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE Integrated Device Technology, Inc. IDT7M1024 FEATURES: • High-density 4K x 36 Synchronous Dual-Port SRAM module • Architecture based on Dual-Port RAM cells — Allows full simultaneous access from both ports • Synchronous operation — 4ns set-up to clock, 1ns hold on all control, data, and address inputs — Data input, address, and control registers — Fast 20ns clock to data out — Self-timed write allows fast write cycle • Clock enable feature • Single 5V (±10%) power supply • Multiple GND pins and decoupling capacitors for maximum noise immunity • Inputs/outputs directly TTL-compatible DESCRIPTION: The IDT7M1024 is a 4K x 36 bit high-speed synchronous Dual-Port Static RAM module constructed on a co-fired ce- ramic substrate using four IDT7099 (4K x 9) Dual-Port RAMs. The IDT7M1024 module is designed to be used as a standalone 36-bit Dual-Port Static RAM. The IDT7M1024 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is independent of the HIGH and LOW periods of the clock. This allows the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. The data inputs are gated to control on-chip noise in bussed applications. The user must guarantee that the R/W pins are LOW for at least one clock cycle before any write is attempted. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. The IDT7M1024 module is packaged in a 142-lead ceramic FUNCTIONAL BLOCK DIAGRAM L_CLK L_CLKENL L_CEL L_OEL L_A0 – 11 L_I/O0 – 8 L_ R/W0 IDT7099 4K x 9 R_CLK R_CLKENL R_CEL R_OEL R_A0 – 11 R_I/O0 – 8 R_ R/W0 L_I/O9 – 17 L_ R/W1 L_CEH L_OEH L_I/O18 – 26 L_ R/W2 L_CLKENH L_I/O27 – 35 IDT7099 4K x 9 L_ R/W3 The IDT logo is a registered trademark of Integrated Device Technology, Inc. R_I/O9 – 17 IDT7099 4K x 9 R_ R/W1 R_CEH R_OEH R_I/O18 – 26 R_ R/W2 R_CLKENH R_I/O27 – 35 IDT7099 4K x 9 R_ R/W3 2809 drw 01 MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. MARCH 1996 DSC-2809/6 7.4 1 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES PGA (Pin Grid Array). All IDT military modules are constructed with semiconductor components manufactured in compliance with the latest revision of MIL-STD-883, Class B making them ideally suited to applications demanding the highest level of performance and reliability. PIN CONFIGURATION 1 A B C D E F G H J K L M N GND L_I/O4 L_I/O8 L_I/O9 L_I/O12 L_I/O13 GND L_I/O14 L_I/.


IDT7M1014 IDT7M1024 IDT7MB4048


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)