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IDT7MPV6255 Dataheets PDF



Part Number IDT7MPV6255
Manufacturers Integrated Device
Logo Integrated Device
Description 256KB AND 512KB SECONDARY CACHE MODULES FOR THE PowerPCO
Datasheet IDT7MPV6255 DatasheetIDT7MPV6255 Datasheet (PDF)

256KB AND 512KB SECONDARY CACHE MODULES FOR THE PowerPC™ Integrated Device Technology, Inc. IDT7MPV6253 IDT7MPV6255/56 FEATURES • For CHRP based PowerPC™ systems. • Asynchronous and pipelined burst SRAM options in the same module pinout • Low-cost, low-profile card edge module with 178 leads • Uses Burndy Computerbus™ connector, part number ELF182KSC-3Z50 • Operates with external PowerPC CPU speeds up to 66MHz • Separate 5V (±5%) and 3.3V (+10/-5%) power supplies • Multiple GND pins and decoup.

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256KB AND 512KB SECONDARY CACHE MODULES FOR THE PowerPC™ Integrated Device Technology, Inc. IDT7MPV6253 IDT7MPV6255/56 FEATURES • For CHRP based PowerPC™ systems. • Asynchronous and pipelined burst SRAM options in the same module pinout • Low-cost, low-profile card edge module with 178 leads • Uses Burndy Computerbus™ connector, part number ELF182KSC-3Z50 • Operates with external PowerPC CPU speeds up to 66MHz • Separate 5V (±5%) and 3.3V (+10/-5%) power supplies • Multiple GND pins and decoupling capacitors for maximum noise immunity • Presence Detect output pins allow the system to determine the particular cache configuration. x 8 asynchronous static RAMs and the IDT7MPV6255/56 use IDT’s 71V432 32K x 32 pipelined synchronous burst static RAMs in plastic surface mount packages mounted on a multilayer epoxy laminate (FR-4) board. In addition, each of the modules uses the IDT 71216 16K x 15 Cache-Tag static RAM and IDT FCT logic. Extremely high speeds are achieved using IDT’s high-reliability, low cost CMOS technology. The low profile card edge package allows 178 signal leads to be placed on a package 5.06" long, a maximum of 0.250" thick and a maximum of 1.08" tall. The module space savings versus discrete components allows the OEM to design additional functions onto the system or to shrink the size of the motherboard for reduced cost. All inputs and outputs are LVTTL-compatible, and operate from separate 5V (±5%) and 3.3V (+10/-5%) power supplies. Multiple GND pins and on-board decoupling capacitors ensure maximum protection from noise. DESCRIPTION The IDT7MPV6253/55/56 modules belong to a family of secondary caches intended for use with PowerPC CPUbased systems. The IDT7MPV6253 uses IDT’s 71V256 32K FUNCTIONAL BLOCK DIAGRAM IDT7MPV6253 – 256KB ASYNCHRONOUS VERSION A14 - A26 ALE ADDRA0 ADDRA1 SRAM OE1 WE#0 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 8 13 Latch 13 PD0 PD1 PD2 ADDRA0 ADDRA1 SRAM OE0 DH0 - DH7 WE#4 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 8 PD3 DL0 - DL7 WE#1 8 DH8 - DH15 WE#5 8 DL8 - DL15 WE#2 8 DH16 - DH23 WE#6 8 DL16 - DL23 WE#3 STANDBY A14 - A26 TWE# TOE# STANDBY TCLR# TVALID DIRTYIN CLK2 13 8 DH24 - DH31 WE#7 STANDBY 12 8 DL24 - DL31 A2 - A13 TMATCH 8K x 12 Tag Field 8K x 2 Status DIRTYOUT drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. PowerPC is a trademark of IBM. Computerbus is trademark of Burndy. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. JUNE 1996 DSC-3608/2 1 IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM IDT7MPV6255 – 256KB PIPELINED BURST VERSION WE#0 WE#1 WE#2 WE#3 CLK 1 CLK0 WE#4 WE#5 WE#6 WE#7 SRAM OE#0 SRAM ADS#0 CNT EN#0 STANDBY BURST MODE A14 - A28 15 32K x 32 Pipelined Burst SRAM 32 DH 0-31 32K x 32 Pipelined Burst SRAM 32 DL0-31 PD0 PD1 PD2 PD3 A14 - A26 TWE# TOE# STANDBY TCLR# TVALID DIRTYIN CLK2 13 12 A2 - A13 TMATCH 8K x 12 Tag Field 8K x 2 Status DIRTYOUT drw 02 RECOMMENDED DC OPERATING CONDITIONS Symbol VCC3 VCC5 GND VIH VIL Parameter Supply Voltage Supply Voltage Supply Voltage Input High Voltage Min. 3.14 4.75 0 2.2 Typ. 3.3 5.0 0 — — Max. 3.6 5.25 0.0 VCC + 0.3 0.8 Unit V V V V V tbl 01 ABSOLUTE MAXIMUM RATINGS Symbol Rating Value –0.5 to +4.6 0 to +70 –10 to +85 –55 to +125 50 Unit V °C °C °C mA VTERM Terminal Voltage with Respect for VCC3 to GND TA TBIAS TSTG IOUT Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Input Low Voltage –0.5(1) NOTE: 1. VIL = –1.0V for pulse width less than 5ns, once per cycle. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Power Plane VCC3 VCC5 Ambient Temperature 0°C to +70°C 0°C to +70°C GND 0V 0V VCC 3.3V +10/-5% 5.0V ± 5% tbl 02 NOTE: tbl 03 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SRAM ACCESS TIMES Module Speed 66MHz Asych 15ns Burst(1) 8.5ns Tag 10ns tbl 04 NOTE: 1. Burst SRAMs are measured by Clock to Data Out (tCD). 2 IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM IDT7MPV6256 – 512KB PIPELINED BURST VERSION WE#0 WE#1 WE#2 WE#3 CLK1 WE#4 WE#5 WE#6 WE#7 CLK0 SRAM OE#0 SRAM ADS#0 CNT EN#0 STANDBY BURST MODE A13 - A28 16 32K x 32 Pipelined Burst SRAM 32 WE#0 WE#1 WE#2 WE#3 CLK1 WE#4 WE#5 WE#6 WE#7 CLK0 32K x 32 Pipelined Burst SRAM 32 DH0-31 32K x 32 Pipelined Burst SRAM 32K x 32 Pipelined Burst SRAM DH0-31 32 32 DL0-31 SRAM OE#1 SRA.


IDT7MPV6253 IDT7MPV6255 IDT7MPV6256


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