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Silicon Bipolar MMIC 3.5 and 5.5 GHz Divide-by-4 Static Prescalers Technical Data
IFD-53010 IFD-53110
Features
• Wide Operating Frequency Range: IFD-53010: 0.15 to 5.5 GHz IFD-53110: 0.15 to 3.5 GHz • Low Phase Noise: -143 dBc/Hz @ 1 kHz Offset • Output Power: -5 dBm Typ. • Single Supply Voltage Vcc = 5 V or Vee = -5 V • On-Chip Terminations Provide Good Input and Output VSWRs • Hermetic Gold-Ceramic Surface Mount Package
100 mil Stripline Package
Description
Hewlett-Packard's IFD-53010 and IFD-53110 are low phase noise silicon bipolar static digital frequency dividers using two scaled Emitter-Coupled-Logic (ECL) master-slave D flip-flops and buffer amplifiers. They are housed in hermetic high reliability surface mount packages suitable for commercial, industrial, and military applications. Typical applications include stabilized or digitally controlled local oscillators for GPS, SATCOM or military receivers, and frequency synthesizers and counters in instrumentation systems. The IFD-53110 is a lower cost selected version of the IFD-53010, and is distinguished by a reduced operating frequency range. The IFD series of frequency dividers is fabricated using Hewlett-Packard's 18 GHz, ft, ISOSAT™-2 silicon bipolar process which uses nitride selfalignment, submicrometer lithography, trench isolation, ionimplantation, gold metallization and polyimide intermetal dielectric and scratch protection to achieve excellent device uniformity, performance, and reliability.
Pin Configuration
3 V
EE
4 RF INPUT
2 RF OUTPUT
1
V CC
Functional Block Diagram
1 VCC
RF INPUT 4
C C
Q Q
C C
Q Q
RF OUTPUT 2
3
VEE
7-151
5965-9115E
Absolute Maximum Ratings
Symbol Vcc - Vee Pdiss P in Tj TSTG Parameter Device Voltage Power Dissipation[2,3] RF Input Power Junction Temperature Storage Temperature Units V mW dBm °C °C Absolute Maximum[1] 8 650 +15 200 -65 to +200
Thermal Resistance[2]: θjc = 107°C/W
Notes: 1, Operation of this device above any one of these parameters may cause permanent damage. 2. Tcase = 25°C. 3. Derate at 9.3 mW/°C for TC ≥ 130°C.
TA = 25°C, ZO = 50 Ω, Vcc - Vee = 5.0 V Symbol FMAX FMAX ICC
Guaranteed Electrical Specifications, IFD-53010 and IFD-53110
Parameters and Test Conditions IFD-53010: Maximum Clock Frequency IFD-53110: Maximum Clock Frequency Pin = -10 dBm (200 mVpp) Pin = -10 dBm (200 mVpp) Units GHz GHz mA Min. 5.5 3.5 35 Typ. 6.0 5.0 43 50 Max.
IFD-53010 and IFD-53110: Supply Current
Typical Design Information, TA = 25°C, Z0 = 50 Ω, Vcc - Vee = 5.0 V, Pin = -10 dBm. All values apply to both IFD-53010 and IFD-53110. ftest is 5 GHz for IFD-53010 and 3 GHz for IFD-53110 (unless otherwise noted).
Symbol F MIN Pin Pout VSWR PN Tr Tf Minimum Clock Input Sensitivity Output Power Input VSWR Output VSWR SSB Phase Noise Output Rise Time, 20% - 80% Output Fall Time, 20% - 80% Parameters and Test Conditions Frequency[1] f = ftest f = 0.15 to ftest f = 0.15 to ftest f = 0.15 to ftest f = 3 GHz, 1 kHz offset f = 5 GHz, 1 kHz offset (IFD-53.