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PCA1626 Dataheets PDF



Part Number PCA1626
Manufacturers NXP
Logo NXP
Description CMOS
Datasheet PCA1626 DatasheetPCA1626 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET PCA16xx series 32 kHz watch circuits with EEPROM Product specification Supersedes data of 1997 Apr 21 File under Integrated Circuits, IC16 1997 Dec 12 Philips Semiconductors Product specification 32 kHz watch circuits with EEPROM FEATURES • 32 kHz oscillator, amplitude regulated with excellent frequency stability • High immunity of the oscillator to leakage currents • Time calibration electrically programmable and reprogrammable (via EEPROM) • A quartz crystal i.

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INTEGRATED CIRCUITS DATA SHEET PCA16xx series 32 kHz watch circuits with EEPROM Product specification Supersedes data of 1997 Apr 21 File under Integrated Circuits, IC16 1997 Dec 12 Philips Semiconductors Product specification 32 kHz watch circuits with EEPROM FEATURES • 32 kHz oscillator, amplitude regulated with excellent frequency stability • High immunity of the oscillator to leakage currents • Time calibration electrically programmable and reprogrammable (via EEPROM) • A quartz crystal is the only external component required • Very low current consumption; typically 170 nA • Detector for silver-oxide or lithium battery voltage levels • Indication for battery end-of-life ORDERING INFORMATION TYPE NUMBER PCA1601U/10 PCA1602T PCA1603U/7 PCA1604U PCA1604U/10 PCA1605U/7 PCA1606U/10 PCA1607U PCA1608U PCA1611U PCA1621U/7 PCA1621U/10 PCA1622U PCA1623U/7 PCA1624U PCA1625U/7 PCA1626U PCA1627U/7 PCA1628U PCA1629U/7 Note PACKAGE(1) NAME − PMFP8 − − − − − − − − − − − − − − − − − − chip on foil plastic micro flat package; 8 leads (straight) chip with bumps on tape chip in tray chip on foil chip with bumps on tape chip on foil chip in tray chip in tray chip in tray chip with bumps on tape chip on foil chip in tray chip with bumps on tape chip in tray chip with bumps on tape chip in tray chip with bumps on tape chip in tray chip with bumps on tape DESCRIPTION PCA16xx series • Stop function for accurate timing • Power-on reset for fast testing • Various test modes for testing the mechanical parts of the watch and the IC. GENERAL DESCRIPTION The PCA16xx series devices are CMOS integrated circuits specially suited for battery-operated, quartz-crystal-controlled wrist-watches, with bipolar stepping motors. VERSION − SOT144-1 − − − − − − − − − − − − − − − − − − 1. Figure 1 and Chapter “Package outline” show details of standard package, available for specified devices and for large orders only. Chapter “Chip dimensions and bonding pad locations” shows exact pad locations for other delivery formats. 1997 Dec 12 2 Philips Semiconductors Product specification 32 kHz watch circuits with EEPROM PINNING SYMBOL VSS TEST OSC IN OSC OUT VDD M1 M2 RESET PIN 1 2 3 4 5 6 7 8 DESCRIPTION ground (0 V) test output oscillator input oscillator output positive supply voltage motor 1 output motor 2 output reset input Customer testing OSC IN OSC OUT 3 4 VSS TEST 1 2 PCA16xx series 8 7 RESET M2 M1 V DD PCA16xxT 6 5 MSA973 Fig.1 Pin configuration, PCA16xxT, (PMFP8). FUNCTIONAL DESCRIPTION AND TESTING Motor pulse The motor pulse width (tP) and the cycle times (tT) are given in Chapter “Available types”. Voltage level detector The supply voltage is compared with the internal voltage reference VLIT and VEOL every minute. The first voltage level detection is carried out 30 ms after a RESET. Lithium mode If a lithium voltage is detected (VDD ≥ VLIT), the circuit will operate in the lithium mode. The motor pulse will be produced with a 75% duty factor. Silver-oxide mode If the voltage level detected is between VLIT and VEOL, the circuit will operate in silver-oxide mode. Battery end-of-life(1) If the battery end-of-life is detected (VDD ≤ VEOL), the motor pulse will be produced without chopping. To indicate this condition, bursts of 4 pulses are produced every 4 s. Power-on reset For correct operation of the Power-on reset the rise time of VDD from 0 V to 2.1 V should be less than 0.1 ms. All resettable flip-flops are reset. Additionally the polarity of the first motor pulse is positive: VM1 − VM2 ≥ 0 V. An output frequency of 32 Hz is provided at RESET (pin 8) to be used for exact frequency measurement. Every minute a jitter occurs as a result of time calibration, which occurs 90 to 150 ms after disconnecting the RESET from VDD. Connecting the RESET to VDD stops the motor pulses leaving them in a HIGH impedance 3-state condition and a 32 Hz signal without jitter is produced at the TEST pin. A debounce circuit protects accidental stoppages due to mechanical shock to the watch (tDEB = 14.7 to 123.2 ms). Connecting RESET to VSS activates Tests 1 and 2 and disables the time calibration. Test 1, VDD > VEOL. Normal function takes place except the voltage detection cycle (tV) is 125 ms and the cycle time tT1 is 31.25 ms. At pin TEST a minute signal is available at 8192 times its normal frequency. Test 2(2), VDD < VEOL. The voltage detection cycle (tV) is 31.25 ms and the motor pulse period (tT2) = 31.25 ms. Test and reset mode are terminated by disconnecting the RESET pin. Test 3, VDD > 5.1 V. Motor pulses with a time period of tT3 = 31.25 ms and n × 122 µs are produced to check the contents of the EEPROM. At pin TEST the motor pulse period signal (tT) is available at 1024 times its normal frequency. The circuit returns to normal operation when VDD < 2.5 V between two motor pulses. (2) Only applicable for types with the battery end-of-life detector. (1) Only available for types with a 1 s motor pulse. 1997 Dec 12 3 Philips Semiconductors.


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