PCA5010

INTEGRATED CIRCUITS DATA SHEET PCA5010 Pager baseband controller Product specification File under Integrated Circuits, IC17 1998 Nov 02 Philips Semiconductors Product specification Pager baseband controller CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 7 7.1 8 9 10 11 12 13 FEATURES ORDERING INFORMATION GENERAL DESCRIPTION BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION General CPU timing Overview on the different clocks used within the PCA5010 Memory organization Addressing I/O facilities Timer/event counters I2C-bus serial I/O Serial interface SIO0: UART 76.8 kHz oscillator Clock correction 6 MHz oscillator Real-time clock Wake-up counter Tone generator Watchdog timer 2 or 4-FSK demodulator, filter and clock recovery circuit AFC-DAC Interrupt system Idle and power-down operation Reset DC/DC converter INSTRUCTION SET Instruction Map LIMITING VALUES EXTERNAL COMPONENTS DC CHARACTERISTICS AC CHARACTERISTICS CHARACTERISTIC CURVES TEST AND APPLICATION INFORMATION 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 16 17 18 19 19.1 19.2 19.3 19.4 20 21 22 14 14.1 14.2 14.3 15 PCA5010 APPENDIX 1: SPECIAL MODES OF THE PCA5010 Overview OTP parallel programming mode Test modes APPENDIX 2: THE PARALLEL PROGRAMMING MODE Introduction General description Entering the parallel programming mode Address space Single byte programming Multiple byte programming High voltage timing OTP test modes Signature b...