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PCA9510 Dataheets PDF



Part Number PCA9510
Manufacturers NXP
Logo NXP
Description Hot swappable I2C and SMBus bus buffer
Datasheet PCA9510 DatasheetPCA9510 Datasheet (PDF)

INTEGRATED CIRCUITS PCA9510; PCA9511 Hot swappable I2C and SMBus bus buffer Product data sheet Supersedes data of 2003 Dec 18 2004 Oct 05 Philips Semiconductors Philips Semiconductors Product data sheet Hot swappable I2C and SMBus bus buffer PCA9510; PCA9511 DESCRIPTION The PCA9510 and PCA9511 are hot swappable I2C and SMBus buffers that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connecte.

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INTEGRATED CIRCUITS PCA9510; PCA9511 Hot swappable I2C and SMBus bus buffer Product data sheet Supersedes data of 2003 Dec 18 2004 Oct 05 Philips Semiconductors Philips Semiconductors Product data sheet Hot swappable I2C and SMBus bus buffer PCA9510; PCA9511 DESCRIPTION The PCA9510 and PCA9511 are hot swappable I2C and SMBus buffers that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9510 and PCA9511 provides bi-directional buffering, keeping the backplane and card capacitances isolated. The PCA9511 rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements, while the PCA9510 has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system. The PCA9510 and PCA9511 incorporate a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW). During insertion, the PCA9510 (IN only) and PCA9511 SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip. The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers allow them to be connected to another PCA9510/11/12/13/14 device in series or in parallel and to the A side of the PCA9517. The PCA9510/11/12/13/14 can not connect to the static offset I/Os used on the PCA9515/15A/16/16A/17 B side and PCA9518. FEATURES • Bi-directional buffer for SDA and SCL lines increases fanout and prevents SDA and SCL corruption during live board insertion and removal from multi-point backplane systems • Compatible with I2C standard mode, I2C fast mode, and SMBus standards • ∆V/∆t rise time accelerators on all SDA and SCL lines (PCA9511 only) • Rise time accelerator threshold of 0.6 V • Active high ENABLE input • Active high READY open-drain output • High impedance SDA and SCL pins for VCC = 0 V • 1 V precharge on all SDA and SCL lines (PCA9510 IN only) • Supports clock stretching and multiple master arbitration/synchronization APPLICATION • cPCI, VME, AdvancedTCA cards and other multi-point backplane cards that are required to be inserted or removed from an operating system. • Operating power supply voltage range: 2.7 V to 5.5 V • 5.5 V tolerant I/Os • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 • Latch-up testing is done to JEDEC Standard JESD78 which • Package offer: SO8, TSSOP8 (MSOP8) ORDERING INFORMATION PACKAGES 8-pin plastic SO 8-pin plastic SO 8-pin plastic TSSOP (MSOP) 8-pin plastic TSSOP (MSOP) TEMPERATURE RANGE –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C ORDER CODE PCA9510D PCA9511D PCA9510DP PCA9511DP TOPSIDE MARK PCA9510 PCA9511 9510 9511 DRAWING NUMBER SOT96-1 SOT96-1 SOT505-1 SOT505-1 exceeds 100 mA Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging. 2004 Oct 05 2 Philips Semiconductors Product data sheet Hot swappable I2C and SMBus bus buffer PCA9510; PCA9511 PIN CONFIGURATION TOP VIEW ENABLE 1 SCLOUT SCLIN GND 2 3 4 8 7 6 5 VCC SDAOUT SDAIN READY PIN DESCRIPTION PIN 1 SYMBOL ENABLE DESCRIPTION Chip enable pin. Grounding this pin puts the part in a low current (<1 µA) mode. It also disables the rise time accelerators, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. Serial clock output to and from the SCL bus on the card. Serial clock input to and from the SCL bus on the backplane. Ground. Connect this pin to a ground plane for best results. This is an open-drain output which pulls LOW when SDAIN and SCLIN are disconnected from SDAOUT and SCLOUT, and turns off when the two sides are connected. Serial data input to and from the SDA bus on the backplane. Serial data output to and from the SDA bus on the card. Power supply. 2 3 SCLOUT SCLIN GND READY SW01045 Figure 1. Pin configuration. 4 5 6 7 8 SDAIN SDAOUT VCC FEATURE SELECTION CHART FEATURES Idle detect High impedance SDA, SCL pins for VCC = 0 V Rise time accelerator circuitry on all SDA and SCL lines Rise time accelerator circuitry hardware disable pin for lightly loaded systems Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin Ready open drain output Two VCC pins to support 5 V to 3.3 V level translation with improved noise margins 1 V precharge on all SDA and SCL lines 92 µA current source on SCLIN and SDAIN for PICMG applications PCA9510 Yes Yes — — — Yes — IN only — PCA9511 Yes Yes Yes — — Yes — Yes — PCA9512 Yes Yes Yes Yes — — Yes Yes — PCA9513 Yes Yes Yes.


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