BU4015BF

Standard ICs Dual 4-bit static shift register BU4015B / BU4015BF The BU4015B and BU4015BF are 4-stage static shift registers, each consisting of two circuits. The D flip-flops for each stage share a common reset input, enabling external asynchronous reset at any point. Also, the flip-flops at each stage are triggered by the rising edge of the clock input. “H” level reset input resets the contents of all stages to “L”, regardless of the clock and data input, and sets data outputs Q0 to Q3 to “L”. Features 1) Low power dissipation. 2) Wide range of operating power supply voltages. 3) High input impedance. 4) High fan-out. 5) Direct drive of 2 L-TTL inputs and 1 LS-TTL input. Block diagram CLOCK B Q3B 1 16 VDD 2 CL Q2B 3 R D 14 RESET B Q0B 15 DB Logic circuit diagram Q0 Q1 Q2 Q3 D D Q D Q D Q D Q CLR Q CLR Q CLR Q CLR Q CLOCK Q3 Q2 Q1 Q0 Q1A 4 13 RESET Q0A RESET A DA 5 Q 0 Q1 Q2 Q3 6 CL R D 12 Q1B Q2B 11 7 10 Q3A CLOCK A VSS 8 9 Truth table CLOCK D L H X X X : Irrelevant RESET L L L H Q0 L H Q1 Q0 Q0 Q2 Q1 Q1 Q3 Q2 Q2 No Change L L L L X 1 Standard ICs BU4015B / BU4015BF = 0V, Ta = 25°C) Symbol VDD Pd Topr Tstg VIN Limits – 0.3 ~ + 18 1000 (DIP), 500 (SOP) – 40 ~ + 85 – 55 ~ + 150 – 0.3 ~ VDD + 0.3 Unit V mW °C °C V Absolute maximum ratings (V Parameter Power supply voltage Power dissipation Operating temperature Storage temperature Input voltage SS Electrical characteristics DC characteristics (unless otherwise noted, Ta = 25°C, V Par...