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PCA9559 Dataheets PDF



Part Number PCA9559
Manufacturers NXP
Logo NXP
Description 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
Datasheet PCA9559 DatasheetPCA9559 Datasheet (PDF)

INTEGRATED CIRCUITS PCA9559 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM Product specification Supersedes data of 1999 Oct 20 2000 Jan 31 Philips Semiconductors Philips Semiconductors Product specification 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM PCA9559 FEATURES •5-bit 2-to-1 multiplexer, 1-bit latch •6-bit internal non-volatile register •Internal non-volatile register programmable and readable via I2C bus •Override input forces all outputs to logic 0 •5 open drain multiplex.

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INTEGRATED CIRCUITS PCA9559 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM Product specification Supersedes data of 1999 Oct 20 2000 Jan 31 Philips Semiconductors Philips Semiconductors Product specification 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM PCA9559 FEATURES •5-bit 2-to-1 multiplexer, 1-bit latch •6-bit internal non-volatile register •Internal non-volatile register programmable and readable via I2C bus •Override input forces all outputs to logic 0 •5 open drain multiplexed outputs •1 open drain non-multiplexed (latched) output •5V and 2.5V tolerant inputs •Useful for ‘jumperless’ configuration of PC motherboards •2 address pins, allowing up to 4 devices on the I2C bus DESCRIPTION The primary function of the 5-bit multiplexer, 1-bit latch is to enable system configuration. PIN CONFIGURATION 2 I C SCL SDA A1 A0 1 2 3 4 5 6 7 8 9 20 VCC 19 WP 18 OVERRIDE # 17 NON_MUXED_OUT 16 MUX_OUT A 15 MUX_OUT B 14 MUX_OUT C 13 MUX_OUT D 12 MUX_OUT E 11 MUX_SELECT I2C MUX_IN A MUX_IN B MUX_IN C MUX_IN D MUX_IN E GND 10 SW00216 ORDERING INFORMATION PACKAGES 20-Pin Plastic TSSOP TEMPERATURE RANGE 0°C to +70°C ORDER CODE PCA9559 PW DH DRAWING NUMBER SOT360-1 FUNCTIONAL DESCRIPTION When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE# signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 1. The Write Protect (WP) input is used to control the ability to write the contents of the 6-bit non-volatile register. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C bus (described in the next section). The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have internal pullup resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures. FUNCTION TABLE OVERRIDE# MUX_SELECT MUX_OUT OUTPUTS All 0’s MUX_IN inputs From nonvolatile register MUX_IN inputs NON_MUXED_OUT OUTPUT All 0’s Latched NON_MUXED_OUT 1 From non-volatile register From non-volatile register 0 0 0 1 1 0 1 1 NOTE: 1. NON_MUXED_OUT state will be the value present on the output at the time of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state. 2000 Jan 31 2 853-2181 23063 Philips Semiconductors Product specification 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM PCA9559 PIN DESCRIPTION PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL I2C SCL I2C SDA A1 Address A0 Address MUX_IN A MUX_IN B MUX_IN C MUX_IN D MUX_IN E GND MUX_SELECT MUX_OUT E MUX_OUT D MUX_OUT C MUX_OUT B MUX_OUT A NON_MUXED_OUT OVERRIDE# WP VCC Open drain outputs from non-volatile memory Forces all outputs to logic 0 Non-volatile register write-protect Positive voltage rail Open drain multiplexed outputs Ground Selects MUX_IN inputs or register contents for MUX_OUT outputs External inputs to multiplexer Serial I2C bus clock Serial bi-directional I2C bus data A1 A0 FUNCTION I2C INTERFACE Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) has 5 fixed bits and two user-programmable bits followed by a 1-bit read/write value which determines the direction of the data transfer. MSB LSB 1 0 0 1 1 A1 A0 R/W# SW00218 Figure 1. I2 C Address Byte Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The four high-order bits are latched outputs, while the four low order bits are multiplexed outputs (Figure 2). NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VCC to the I2C bus is powered down or VCC to the component is dropped below normal operating levels. MSB LSB 0 0 Non_muxed Data Mux Data E Mux Data D Mux Data C Mux Data B Mux Data A SW00456 Figure 2. I2C Data Byte 2000 Jan 31 3 Philips Semiconductors Product specification 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM PCA9559 BLOCK DIAGRAM 10–30k Ω MUX_SELEC.


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