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UPA1724 Dataheets PDF



Part Number UPA1724
Manufacturers NEC
Logo NEC
Description SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE
Datasheet UPA1724 DatasheetUPA1724 Datasheet (PDF)

DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA1724 SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE 5 DESCRIPTION The µPA1724 is N-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and so on. 8 PACKAGE DRAWING (Unit : mm) 5 1,2,3 ; Source ; Gate 4 5,6,7,8 ; Drain FEATURES • 2.5-V gate drive and low on-resistance RDS(on)1 = 11.0 mΩ MAX. (VGS = 4.5 V, ID = 5.0 A) 1.44 5 RDS(on)2 = 12.0 mΩ MAX. (VGS = 4.0 V, ID = 5.0 A) 1.8 MAX. 1 5.37 MAX. .

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DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA1724 SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE 5 DESCRIPTION The µPA1724 is N-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and so on. 8 PACKAGE DRAWING (Unit : mm) 5 1,2,3 ; Source ; Gate 4 5,6,7,8 ; Drain FEATURES • 2.5-V gate drive and low on-resistance RDS(on)1 = 11.0 mΩ MAX. (VGS = 4.5 V, ID = 5.0 A) 1.44 5 RDS(on)2 = 12.0 mΩ MAX. (VGS = 4.0 V, ID = 5.0 A) 1.8 MAX. 1 5.37 MAX. 4 6.0 ±0.3 4.4 +0.10 –0.05 0.8 RDS(on)3 = 15.0 mΩ MAX. (VGS = 2.5 V, ID = 5.0 A) • Low Ciss: Ciss = 1850 pF TYP. • Built-in G-S protection diode • Small and surface mount package (Power SOP8) 0.15 0.05 MIN. 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ORDERING INFORMATION PART NUMBER PACKAGE Power SOP8 µPA1724G ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) Drain Current (pulse) Note1 Note2 EQUIVALENT CIRCUIT Drain VDSS VGSS ID(DC) ID(pulse) PT Tch Tstg 20 ±12 ±10 ±40 2.0 150 –55 to +150 V V A A W °C °C Gate Protection Diode Source Gate Body Diode Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 % 2. Mounted on ceramic substrate of 1200 mm x 2.2 mm Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. 2 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G14048EJ1V0DS00 (1st edition) Date Published January 2000 NS CP(K) Printed in Japan The mark 5 shows major revised points. © 1999, 2000 µ PA1724 ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.) CHARACTERISTICS Drain to Source On-state Resistance SYMBOL RDS(on)1 RDS(on)2 RDS(on)3 Gate to Source Cut-off Voltage Forward Transfer Admittance Drain Leakage Current Gate to Source Leakage Current Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge VGS(off) | yfs | IDSS IGSS Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr TEST CONDITIONS VGS = 4.5 V, ID = 5.0 A VGS = 4.0 V, ID = 5.0 A VGS = 2.5 V, ID = 5.0 A VDS = 10 V, ID = 1 mA VDS = 10 V, ID = 5.0 A VDS = 20 V, VGS = 0 V VGS = ±12 V, VDS = 0 V VDS = 10 V VGS = 0 V f = 1 MHz ID = 5.0 A VGS(on) = 4.5 V VDD = 10 V RG = 10 Ω ID = 10 A VDD = 16 V VGS = 4.5 V IF = 10 A, VGS = 0 V IF = 10 A, VGS = 0 V di/dt = 100 A / µs 1850 610 320 43 170 90 130 18 3.2 7.8 0.78 45 40 0.5 10.0 MIN. TYP. 8.6 8..


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