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UPC8102T Dataheets PDF



Part Number UPC8102T
Manufacturers NEC
Logo NEC
Description RF AMPLIFIER IC FOR 150 MHz TO 330 MHz PAGER SYSTEM
Datasheet UPC8102T DatasheetUPC8102T Datasheet (PDF)

DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC8102T RF AMPLIFIER IC FOR 150 MHz TO 330 MHz PAGER SYSTEM DESCRIPTION µPC8102T is a silicon monolisic integrated circuit designed as RF amplifier for 150 MHz to 330 MHz pager system. Due to 1 V supply voltage, this IC is suitable for low voltage pager system. The package is a 6 pin mini mold suitable for high-density surface mounting. This IC is manufactured using NEC’s 20 GHz fT NESATTM III silicon bipolar process. This process uses silicon ni.

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DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC8102T RF AMPLIFIER IC FOR 150 MHz TO 330 MHz PAGER SYSTEM DESCRIPTION µPC8102T is a silicon monolisic integrated circuit designed as RF amplifier for 150 MHz to 330 MHz pager system. Due to 1 V supply voltage, this IC is suitable for low voltage pager system. The package is a 6 pin mini mold suitable for high-density surface mounting. This IC is manufactured using NEC’s 20 GHz fT NESATTM III silicon bipolar process. This process uses silicon nitride passivation film and gold electrodes. These materials contribute excellent DC, AC performance. Thus, this process is utilized for 1 V voltage IC. FEATURES • 1 V supply voltage: VCC = 0.9 V to 2.0 V • Low noise figure: 2.3 dBTYP. @ fin = 150 MHz (with external matching circuit to optimize NF) • Low current consumption: ICC = 0.5 mATYP. @ VCC = 1.0 V • Gain available frequency: fRF = 150 MHz to 330 MHz (with external matching circuit) • High-density surface mounting: 6 pin mini mold ORDERING INFORMATION PART NUMBER PACKAGE 6 pin mini mold MARKING C2B SUPPLYING FORM Embossed tape 8 mm wide. Pin 1, 2, 3 face to perforation side of tape. QTY 3 kp/Reel µPC8102T-E3 * For evaluation sample order, please contact your local NEC sales office. (Order number: µPC8102T). PIN CONNECTIONS (Top View) 3 2 1 (Bottom View) 4 5 6 4 5 6 3 2 1 1: 2: 3: 4: 5: 6: INPUT GND OUTPUT VCC C1 C2 C2B Caution Electro-static sensitive devices Document No. P11501EJ2V0DS00 (Previous No. ID-3534) Date Published May 1996 P Printed in Japan © 1996 µPC8102T INTERNAL BLOCK DIAGRAM 3 4 2 5 1 6 SYSTEM APPLICATION EXAMPLE AS PAGER 150 MHz to 330 MHz µ PC8102T µ PC8103T BPF BPF IF 2 µPC8102T PIN EXPLANATION SUPPLY VOLTAGE (V) — PIN VOLTAGE (V) 0.75 PIN NO. NAME FUNCTION AND APPLICATION EQUIVALENT CIRCUIT 1 INPUT RF signal input pin. This pin should be externally equipped with matching circuit in accordance with desired frequency. This ground pin must be connected to the system ground with minimum inductance. Ground pattern on the board should be formed as wide as possible. Track length should be kept as short as possible. Amplified signal output pin. This pin should be externally equipped with matching circuit in accordance with desired frequency. 2 GND 0 — 3 1 3 OUTPUT C2 pin voltage must be applied through external matching inductor VCC 0.9 to 2.0 — 2 6 5 4 4 — Supply voltage pin. Connect bypass capacitor (eg 1000 pF) to minimize ground impedance. Ground with capacitance pin (eg 1000 pF). AC ground pin for output 5 C1 — 0.88 6 C2 — 0.85 Note Pin voltage values are described at VCC = 1 V. 3 µPC8102T ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Power Dissipation SYMBOL VCC PD TA = +25 ˚C Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass PWB at TA = +85 ˚C CONDITION RATINGS 2.2 280 UNIT V mW Operating Temperature Storage Temperature Topt Tstg –40 to +85 –55 to +150 ˚C ˚C RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Operating Temperature Operating Frequency SYMBOL VCC Topt fopt MIN. 0.9 –40 150 TYP. 1.0 +25 MAX. 2.0 +85 330 UNIT V ˚C MHz Electric characteristic (TA = +25 ˚C, VCC = 1.0 V, ZS = ZL = 50 Ω) PARAMETER Circuit Current Power Gain Output 3rd order intercept point SYMBOL ICC GP OIP3 TEST CONDITIONS MIN. No input signal, TEST CIRCUIT 1 f = 280 MHz, TEST CIRCUIT 3 f1 = 150.000 MHz, f2 = 150.025 MHz TEST CIRCUIT 2 0.30 10.0 — µPC8102T TYP. 0.5 13.5 –5 MAX. 0.65 16.5 — UNIT mA dB dBm Note External matching circuits should be attached to input and output pins. Standared characteristics for reference (Sample: ICC = 0.55 mA, Condition: TA = +25 ˚C, VCC = 1.0 V) PARAMETER matched with 50 Ω Power Gain 1 Noise Figure 1 Power Gain 2 Noise Figure 2 Power Gain 3 Noise Figure 3 matched to optimize NF Power Gain 4 Noise Figure 4 Power Gain 5 Noise Figure 5 Power Gain 6 Noise Figure 6 GP 4 NF4 GP 5 NF5 GP 6 NF6 f = 330 MHz, TEST CIRCUIT 6 f = 280 MHz, TEST CIRCUIT 4 f = 150 MHz, TEST CIRCUIT 2 19.4 2.3 14.0 2.9 11.6 3.1 dB dB dB dB dB dB GP 1 NF1 GP 2 NF2 GP 3 NF3 f = 330 MHz, TEST CIRCUIT 5 f = 280 MHz, TEST CIRCUIT 3 f = 150 MHz, TEST CIRCUIT 2 20.6 3.6 14.7 4.0 14.5 4.1 dB dB dB dB dB dB SYMBOL CONDITIONS Reference value UNIT 4 µPC8102T TEST CIRCUIT 1 1 2 3 IN GND OUT C2 6 C1 5 VCC 4 A 5 µPC8102T TEST CIRCUIT 2 (150 MHz) 7.5 pF (Note) 1 2 3 7.5 pF (Note) 10 pF 47 kΩ IN 68 nH 10 pF 1 000 pF C2 6 GND OUT 84 nH 1 000 pF C1 5 VCC 4 1 000 pF 1 000 pF Note Matching can be adjusted with trimmer condenser. ILLUSTRATION OF THE TEST CIRCUIT 2 ASSEMBLED ON EVALUATION BOARD 10 pF OUT 7.5pF 1 000 pF 84 nH 1 000 pF 3 2 1 C2B 47k Ω VCC 4 5 6 10 pF 7.5pF IN 68 nH 8102/07 1 000 pF 1 000 pF 1 000 pF Mounting direction Note (*1) 35 × 42 × 0.4 mm double copper clad polyimide board (*2) Back side: GND pattern (*3) Solder plated on pattern (*4) : Through holes 6 µPC8102T TEST CIRCUIT 3 (280 MHz)


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