Document
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC8105GR
400 MHz QUADRATURE MODULATOR FOR DIGITAL MOBILE COMMUNICATION
DESCRIPTION
The µPC8105GR is a sillicon monolithic integrated circuit designed as quadrature modulator for digital mobile communication systems. This modulator housed in a 16 pin plastic SSOP that is easy to install and contributes to miniaturizing the system. The device has power save function and can operates 2.7 to 5.5 V supply voltage to realize low power consumption.
FEATURES
• • • • •
Internal 90° phase shifter is accurate over an IF range from 100 MHz to 400 MHz. Wide supply voltage range: VCC = 2.7 to 5.5 V. Low operation current: ICC = 16 mA (typ.). 16 pin plastic SSOP suitable for high density surface mounting. Low current in sleep mode
APPLICATION
• •
IF modulator for Digital cellular phone (PDC, IS-54, GSM etc..) IF modulator for Digital cordless phone (PHS, PCS etc..)
ORDERING INFORMATION
PART NUMBER PACKAGE 16 pin plastic SSOP (225 mil) SUPPLYING FORM Carrier tape width 12 mm. Q’ty 2.5 kp/Reel Pin 1 indicated pull-out direction of tape.
µPC8105GR-E1
To order evaluation samples, please contact your local NEC sales office.
(Part number for sample order:
µPC8105GR)
Caution electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. P10807EJ3V0DS00 (3rd edition) Date Published October 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
©
1995, 1999
µPC8105GR
SERIES PRODUCTS
PART NUMBER f LO1 in (MHz) 100 to 300 f MODout (MHz) 50 to 150 f I/Q (MHz) DC to 0.5 Up-Converter f RFout (MHz) External
SERIES TYPE 150 MHz Quadrature MOD Up-Con + Quadrature MOD 400 MHz Quadrature MOD
APPLICATIONS CT2, Digital Comm.
µPC8101GR µPC8104GR µPC8105GR
100 to 400 100 to 400
DC to 10 DC to 10
800 to 1900 External
Digital Comm. Digital Comm.
Remark: As for detail information of series products, please refer to each data sheet.
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)
LOin 1 LOin 2 GND 3 I-INPUT 4 I-INPUT 5 Q-INPUT 6 Q-INPUT 7 GND 8 90˚ Phase Sifter REG.
16 VCC 15 Power Save 14 GND 13 GND 12 MODout 11 N.C. 10 N.C. 9 N.C.
APPLICATION EXAMPLE
[Digital cellular hand-held phone]
Low-noise transistor RX DEMO I Q
VCO SW
÷N
PLL PLL
µ PC8105GR
I 0˚ TX PA Phase shifter
µ PC8106T
90˚ Q
2
Data Sheet P10807EJ3V0DS00
µPC8105GR
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Power Save Voltage Power Dissipation Operating Temperature Storage Temperature SYMBOL VCC VPS PD Top Tstg RATING 6.0 6.0 310 −40 to +85 −55 to +150 UNIT V V mW °C °C TEST CONDITIONS TA = +25 °C TA = +25 °C TA = +85 °C
*1
*1: Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass board RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage Operating Temperature Modulator Output Frequency LO1 Input Frequency I/Q Input Frequency SYMBOL VCC TA fMODout fLO1in fI/Qin DC 10 MHz MIN. 2.7 −40 100 TYP. 3.0 +25 MAX. 5.5 +85 400 UNIT V °C MHz PLOin = −10 dBm PI/Qin = 600 mVp-p MAX (Single ended) TEST CONDITIONS
ELECTRICAL CHARACTERISTICS (TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS ≥ 1.8 V)
PARAMETER Circuit Current Circuit Current at Power Save Mode Output Power LO Carrier Leak Image Rejection (Side Band Leak) SYMBOL ICC ICC(PS) −21.0 MIN. 10 TYP. 16 0.1 −16.5 −40 −40 MAX. 21 5 −12.0 −30 −30 UNIT mA TEST CONDITIONS No input signal VPS ≤ 1.0 V
µA
dBm dBc dBc
PMODout LOL ImR
I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended)
Data Sheet P10807EJ3V0DS00
3
µPC8105GR
STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS ≥ 1.8 V)
PARAMETER I/Q 3rd Order Intermodulation Distortion I/Q Input Impedance I/Q Bias Current LO1 Input VSWR Power Save Rise Time Power Save Fall Time SYMBOL IM3I/Q MIN. TYP. −50 MAX. −30 UNIT dBc kΩ TEST CONDITIONS I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) (I → I, Q → Q)
ZI/Q II/Q ZLO TPS(RISE) TPS(FALL)
20 5 1.2:1 2 2 5 5
µA
−
µs µs
VPS(OFF) → VPS(ON) VPS(ON) → VPS(OFF)
4
Data Sheet P10807EJ3V0DS00
µPC8105GR
PIN EXPLANATION
ASSIGNMENT LOin SUPPLY VOL. (V) − PIN VOL.(V) 0
PIN NO. 1
FUNCTION AND APPLICATION LO input for phase shifter. This input impedance is 50 Ω matched internally. Bypass of LO input. This pin is grounded through internal capacitor. Open in case of single ended. Connect to the ground with minimum inductance. Track length should be kept as short as possible. Input for I signal. This in put impedance is larger than 20 kΩ. Relations between amplitude and VCC/2 bias of input signal are following. VCC/2 (v) ≥ 1.35 ≥ 1.5 ≥ 1.75 Amp. (mVp-p) *1 400 600 1000
4
EQUIPMENT CIRCUIT
1 50 Ω
2
LOin
−
2.4
2
3
GND
0
−
8 −
4
I
VCC/2
5
5
I
VCC/2
−
Input for I .