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INTEGRATED CIRCUITS
DATA SHEET
PCF5077T Power amplifier controller for GSM and PCN systems
Preliminary specification File under Integrated Circuits, IC17 1997 Nov 19
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
FEATURES • CMOS low-voltage, low-power • Can be used in burst mode with power-down • 3-wire serial bus interface with the bus available in Power-down mode • On-chip ramp generator for 256 different power levels with two dynamic ranges • Two programmable regulator start conditions (VKICK and VHOME) • Programmable analog output voltage limitation • Ramping speed depending on the 13 MHz system frequency clock for Global System for Mobile communications (GSM) and Personal Communications Network (PCN) • Low swing input buffer for the 13 MHz master clock • Compatible to a large number of different RF power modules QUICK REFERENCE DATA SYMBOL VDDD VDDA1 VDDA2 IDD(oper)(tot) Tamb Notes PARAMETER digital supply voltage analog supply voltage 1 analog supply voltage 2 (for OP4) total operating current on the VDD pins operating ambient temperature note 2 CONDITIONS note 1 note 1 MIN. 2.7 2.7 2.7 − −40 TYP. 3.0 3.0 5.0 9 −
PCF5077T
• Programmable temperature matching • Dual supply concept for analog and digital part • No external filter for suppression of clock pulse feed through • Direct power control with ramping function (control loop can be switched off) • On-chip Power-on reset for all registers • Serial bus is compatible to bus systems independent of additional clock pulse after rising edge of strobe signal • Low operating current consumption • TTL compatible interface • Programmable gain factor for sensor signal at OP1 • Two different voltages for 1 LSB of the burst power Digital-to-Analog Converter (DAC) are programmable.
MAX. 6.0 6.0 6.0 18 +85
UNIT V V V mA °C
1. The voltages VDDA1 and VDDD must be equal and VDDA2 must be either equal or greater than VDDA1 = VDDD. 2. VDDA1 = VDDD = 3 V and VDDA2 = 5 V. The VDD pins are: VDDA1, VDDA2 and VDDD. ORDERING INFORMATION TYPE NUMBER PCF5077T PACKAGE NAME SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm VERSION SOT369-1
1997 Nov 19
2
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
BLOCK DIAGRAM
PCF5077T
handbook, full pagewidth
RF input (sensor)
C2
voltage control for RF power module D1 R1 C1 VS 1 RF-ZERO + DC C6 BVS 4 VINT(N) 15 VINT(O) 14
VD1
BAND GAP VDDA1 Ibias Vref 8 DAC8 DACA QRSA −0.8 100 mV DACA POWER LEVEL REGISTER 8-bit KICKA VKICK REGISTER VHOME REGISTER LIMITER REGISTER DF0/1, DC, DR0/1, TEST 6-bit 6 + 2-bit 2-bit 6 −0.33 +0.33 SC-ADDER KICKA QRSA Vref 30 µA C4 10 pF R2 1 kΩ
4.8 pF C5 19.2 pF R3 OP1 3.5 kΩ DR1 R4 8.4 kΩ HPA + DC
Vref
DR0 HPA R5 5 kΩ Vref
OP4
SLOPE GENERATOR
ANALOG FILTER Vref
R8 2.8 kΩ
R9 2.8 kΩ
COMPARATOR
R10 DAC6 4.2 kΩ
HPA + DC
INPUT BUFFER
PCF5077T
SERIAL BUS INTERFACE
1/6
CONTROL
2 DF
9 STROBE
10 CLK
11 DATA
13 VSSA
12
3
16
6 VDDD
8 CLK13
5 TRIG
7
MGK910
VDDA1 VSSD VDDA2
PD
Fig.1 Block diagram.
1997 Nov 19
3
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and PCN systems
PINNING SYMBOL VS DF VDDA1 BVS TRIG VDDD PD CLK13 STROBE CLK DATA VSSD VSSA VINT(O) VINT(N) VDDA2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION sensor signal input programmable 3-state output analog supply voltage 1 buffered sensor signal output trigger signal input digital supply voltage power-down input (active LOW) 13 MHz master clock input (low-swing) serial bus strobe signal input serial bus clock signal input serial bus data signal input digital ground analog ground integrator output integrator inverting input analog supply voltage 2 (for OP4)
handbook, halfpage
PCF5077T
VS 1 DF 2 VDDA1 3 BVS 4
16 VDDA2 15 VINT(N) 14 VINT(O)
PCF5077T
TRIG 5 VDDD 6 PD 7 CLK13 8
MGK909
13 VSSA 12 VSSD 11 DATA 10 CLK 9 STROBE
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION General This CMOS device integrates operational amplifiers, two digital-to-analog converters and a serial bus interface to implement an ‘Integrating-Controller’ (see Fig.1). It is designed to control both the power level and the up- and down-ramping of GSM/PCN transmit bursts. The GSM/PCN power-up and power-down ramping curves are generated on-chip, using an internal clock frequency of 1 2.166 MHz T cy = ------ , that is generated internally by f clk dividing the external 13 MHz clock signal by six. Generally, the power amplifier is ramped-up after a rising edge on pin TRIG and ramped-down after a falling edge. The content of the power level register (bits PL7 to PL0) determines which of the 2 × 256 possible values the top of the burst will have. To match the controller to different power modules and sensors several parameters must be adapted. The following parameters influence the performance of the transmission system: • The external capacitor C1 in Fig.1 d.