Document
DATA SHEET
MOS INTEGRATED CIRCUIT
PD16312
1/4- to 1/11-DUTY FIPTM (VFD) CONTROLLER/DRIVER
The PD16312 is a FIP (fluorescent Indicator Panel, or Vacuum Fluorescent Display) controller/driver that is driven on a 1/4- to 1/11 duty factor. It consists of 11 segment output lines, 6 grid output lines, 5 segment/grid output drive lines, a display memory, a control circuit, and a key scan circuit. Serial data is input to the PD16312 through a three-line serial interface. This FIP controller/driver is ideal as a peripheral device for a single-chip microcomputer.
FEATURES
• Multiple display modes (11-segment & 11-digit to 16-segment & 4-digit) • Key scanning (6 4 matrix) • Dimming circuit (eight steps) • High-voltage output (VDD 35 V max). • LED ports (4 chs., 20 mA max). • General-purpose input port (4 bits) • No external resistors necessary for driver outputs (P-ch open-drain + pull-down resistor output) • Serial interface (CLK, STB, DIN, DOUT)
ORDERING INFORMATION
Part Number Package 44-pin plastic QFP ( 10)
PD16312GB-3B4
Document No. IC-3307 (1st edition) Date Published March 1997 P Printed in Japan
©
1993
PD16312
BLOCK DIAGRAM
Command decoder
Dimming circuit
DIN DOUT Serial I/F CLK STB VDD R OSC Timing generator key scan Data selector 5
Seg1 16-bit 16 output latch 5 11 Segment driver Seg11
Display memeory 16 bits × 11 words
Multip lexed diver
Seg12/Grid11
Seg16/Grid7
Key data memory (4 × 6) Key1 to Key4
11-bit shift register 11
5 Grid1 6 Grid driver Grid6
4
SW1 to SW4
4-bit latch 4 4-bit latch LED1 LED4 Key data memory (4 × 6) VDD (+5 V) VSS VEE (0 V) (−30 V)
2
PD16312
PIN CONFIGURATION (Top View)
LED1 LED2 LED3 LED4 Grid1 Grid2 Grid3 35 Grid4 34 33 32 31 30 29 28 27 26 25 24 23 OSC
44
43
42
41
40
39
38
VDD
VSS
37
SW1 SW2 SW3 SW4 DOUT DIN VSS CLK STB KEY1 KEY2
1 2 3 4 5 6 7 8 9
36
Grid5 Grid6 Seg16/Grid7 Seg15/Grid8 Seg14/Grid9 Seg13/Grid10 VEE Seg12/Grid11 Seg11 Seg10 Seg9
10 11
12
13
14
15
16
17
18
19
20
21 Seg7
Seg1/KS1
Seg2/KS2
Seg3/KS3
Seg4/KS4
Seg5/KS5
Seg6/KS6
KEY3
KEY4
Use all power pins.
Seg8
VDD
22
3
PD16312
Pin Function
Symbol DIN Pin Name Data input Pin No 6 Description Input serial data at rising edge of shift clock, starting from the low order bit. Output serial data at the falling edge of the shift clock, starting from low order bit. This is N-ch open-drain output pin. Initializes serial interface at the rising or falling edge of the
DOUT
Data output
5
STB
Strobe
9
PD16312. It then waits for reception of a command. Data input
after STB has fallen is processed as a command. While command data is processed, current processing is stopped, and the serial interface is initialized. While STB is high, CLK is ignored. CLK Clock input 8 Reads serial data at the rising edge, and outputs data at the falling edge. Connect resistor to this pin to determine the oscillation frequency to this pin. Segment output pins (Dual function as key source)
OSC
Oscillator pin
44
Seg1/KS1 to Seg6/KS6 Seg7 to Seg11
High-voltage output
15 to 20
High-voltage output (segment) High-voltage output (grid) High-voltage output (segment/grid) LED output Key data input Switch input Logic power Logic ground Pull-down level
21 to 25
Segment output pins
Grid1 to Grid6 Seg12/Grid11 to Seg16/Grid7 LED1 to LED4 KEY1 to KEY4 SW1 to SW4 VDD VSS VEE
37 to 32 26, 28 to 31
Grid output pins These pins are selectable for segment or grid driving.
42 to 39 10 to 13 1 to 4 14, 38 7, 43 27
CMOS output. +20 mA max. Data input to these pins is latched at the end of the display cycle. These pins constitute a 4-bit general-purpose input port. 5 V 10 % Connect this pin to system GND. VDD 35 V max.
4
PD16312
Display RAM Address and Display Mode The display RAM stores the data transmitted from an external device to the PD16312 through the serial interface, and is assigned addresses as follows, in 8 bits unit:
Seg1 00HL 02HL 04HL 06HL 08HL 0AHL 0CHL 0EHL 10HL 12HL 14HL Seg4 00HU 02HU 04HU 06HU 08HU 0AHU 0CHU 0EHU 10HU 12HU 14HU Seg8 Seg12 01HL 03HL 05HL 07HL 09HL 0BHL 0DHL 0FHL 11HL 13HL 15HL Seg16 01HU 03HU 05HU 07HU 09HU 0BHU 0DHU 0FHU 11HU 13HU 15HU DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8 DIG9 DIG10 DIG11
b0 xxHL
b3 b4 xxHU
b7
Lower 4 bits
Higher 4 bits
5
PD16312
Key Matrix and Key-Input Data Storage RAM The key matrix is made up of a 6 4 matrix, as shown below.
KEY1 KEY2 KEY3 KEY4
Seg1/KS1
Seg2/KS2
Seg3/KS3
Seg4/KS4
Seg5/KS5
The data of each key is stored as illustrated below, and is read with the read command, starting from the least significant bit.
KEY1…KEY4 Seg1/KS1 Seg3/KS3 Seg5/KS5 b0------------ b3 KEY1…KEY4 Seg2/KS2 Seg4/KS4 Seg6/KS6 b4 ------------b7 Reading sequence
LED Port Data is written to the LED port with the write command, starting from the least port’s least significant bit. When a bit of this port is 0, the corresponding LED lights; when the bit is 1, the LED truns off. The data of bits 5 through 8 are ignored.
MSB −.