DatasheetsPDF.com

UPD16435A Dataheets PDF



Part Number UPD16435A
Manufacturers NEC
Logo NEC
Description DOT MATRIX LCD CONTROLLER/DRIVER
Datasheet UPD16435A DatasheetUPD16435A Datasheet (PDF)

DATA SHEET µPD16435, 16435A DOT MATRIX LCD CONTROLLER/DRIVER MOS INTEGRATED CIRCUIT DESCRIPTION The µPD16435 and 16435A are controllers/drivers for a 119 × 73-dot LCD, and perform LCD full-dot and character composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. A charge pump type DC/DC converter is also incorporated, enabling 3 or 5 V single power supply drive. The µPD16435 uses an external reference clock. The µPD16435A has the on-chip oscillation circuit (.

  UPD16435A   UPD16435A


Document
DATA SHEET µPD16435, 16435A DOT MATRIX LCD CONTROLLER/DRIVER MOS INTEGRATED CIRCUIT DESCRIPTION The µPD16435 and 16435A are controllers/drivers for a 119 × 73-dot LCD, and perform LCD full-dot and character composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. A charge pump type DC/DC converter is also incorporated, enabling 3 or 5 V single power supply drive. The µPD16435 uses an external reference clock. The µPD16435A has the on-chip oscillation circuit (external crystal resonator). FEATURES • Can interface to 4 or 8-bit CPU. • Incorporates 119 segment outputs and 73 common outputs. (Display duty selectable from 1/35, 1/37, 1/71, 1/73) • 5 × 7 character font 208 character data configuration character generation ROM and 16 character data configuration character generation RAM, allowing composite full-dot and character display • Incorporates extended display functions such as magnification, lateral scrolling, blink, reverse, etc. • Operating voltage: 2.7 V to 5.5 V • On-chip DC/DC converter: Selectable between ×4 set-up circuit and ×2 step-up circuit • On-chip temperature correction circuit • Master/slave operation capability • On-chip power-on reset circuit • On-chip oscillation circuit (µPD16435A) • 232-pin TCP (Tape Carried Package) ORDERING INFORMATION Part Number Package TCP (TAB), Standard ROM code Standard quad TCP (Conforms to EIAJ), Standard ROM code Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code TCP (TAB), Standard ROM code Standard quad TCP (Conforms to EIAJ), Standard ROM code Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code µPD16435N-001- ××× µPD16435N-001-001 µPD16435N-001-002 µPD16435AN-001-××× µPD16435AN-001-001 µPD16435AN-001-052 Explanation of Part Number µPD16435 (A) N-xxx-xxx TCP code ROM code The TCP model is a custom model. For details, consult NEC sales representative. Document No. S10298EJ3V0DS00 (3rd edition) Date Published April 1997 N Printed in Japan © 1995 µPD16435, 16435A BLOCK DIAGRAM SEG119 COM73 OSC2 COM1 OSC1 SEG1 OSC Common Driver Segment Driver Timing Generator 73-Bit Shift Register 119-Bit Latch Scaler 119 Cursor Blinking Control Register Selector OSC3 Scroll RAM 13 × 73 Bits Display RAM 119 × 73 Bits CGROM 5 × 7 × 208 Bits 5 CGRAM 5 × 7 × 16 Bits Instruction Decoder 8 8 8 Instruction Register Data Register Busy Flag OP-Amp 8 Parallel I/F ×2/×4 Step-Up Circuit 8 GND1 C3+ C3– VCC WR BUSY RESET TEST1 SYNC WS D0~7 SCR C2+ C2– VDD RS RD CS 3/5 TEST2 2 GND2 C1+ C1– VIN+ – VIN 8 V1 V2 V3 V4 V5 Address Counter 7 5 119 73 SEG30 Dummy5 COM73 Dummy3 Dummy4 SEG1 Dummy13 Dummy1 Dummy2 COM38 COM39 79 1 258 80 PIN CONFIGURATION (CHIP) Dummy14 SEG31 SEG32 SEG83 SEG84 Dummy15 135 214 µPD16435, 16435A 136 Dummy26 VDD GND1 CS RS RD WR WS D0 D1 D2 D3 D4 D5 D6 D7 RESET SCR BUSY SYNC TEST1 TEST2 3/5 OSC1 OSC2 OSC3 VCC Dummy25 C1– C1+ C2– C2+ C3– C3+ VIN(–) VIN(+) GND2 V1 V2 V3 V4 V5 Dummy24 Dummy23 215 SEG85 Dummy16 Dummy17 SEG119 COM37 Dummy20 Dummy22 Dummy21 COM1 COM2 3 µPD16435, 16435A PIN DESCRIPTIONS Pin Name CS RS Pin No. 255 254 Input/Output Input Input Output Type ––– ––– Chip select signal Register selection signal (specifies address register when “0”, control register when “1”). Read enable signal. Reads write address when scrolling. Active edge is falling edge. Write enable signal. Active edge is falling edge. Word length selection signal (4-bit input when “1”, 8-bit input when “0”). Transmit/receive data (3-state bidirectional) Upper → D4 to D7 Lower → D0 to D3 (These pins should be set as unused in case of 4-bit data). In test mode, these pins are output pins. In a 4-bit transfer, storage is performed in the upper (MSB) in order from the data transferred first. “0” indicates busy state. “0” → Initialization of all internal registers and commands is performed. Output is fixed at V1. Signal is output to CPU on completion of one-character scroll. Synchronization signal input/output pins for master/slave operation. Description RD 253 Input (Schmitt) ––– WR 252 Input (Schmitt) ––– WS 251 Input ––– D0 to D7 250 to 243 Input/output CMOS 3-state BUSY RESET SCR SYNC 240 242 241 239 Output Input Output Input/output Nch open-drain ––– CMOS Nch open-drain OSC1 OSC2 235 234 ––– ––– µPD16435: Input the 4.19 MHz reference clock to the OSC1 pin externally. Leave the OSC2 pin open. (Always outputs high level.) µPD16435A: This is the pin to which the 4.19 MHz crystal resonator is connected. Input the external clock to OSC1 first. 2 Hz external clock input pin. Scaled by 2 internally to generate 1 Hz, used as blink synchronization signal. Common output signals OSC3 COM1 to COM73 SEG1 to SEG119 TEST1 TEST2 233 212 to 176 3 to 38 41 to 70 81 to 134 137 to 171 238 237 Input (Schmitt) ––– Output Analog switch Output Analog switch Segment output signals “1” → Test mode “0” or open → Normal operating mode Output ––– 4 µP.


UPD16435 UPD16435A UPD16448A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)