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UPD16750 Dataheets PDF



Part Number UPD16750
Manufacturers NEC
Logo NEC
Description 384-OUTPUT TFT-LCD SOURCE DRIVER
Datasheet UPD16750 DatasheetUPD16750 Datasheet (PDF)

DATA SHEET MOS INTEGRATED CIRCUIT µ PD16750 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES) DESCRIPTION The µ PD16750 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules. Because the output dynamic rang.

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DATA SHEET MOS INTEGRATED CIRCUIT µ PD16750 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES) DESCRIPTION The µ PD16750 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules. Because the output dynamic range is as large as VDD2 − 0.2 V to VSS2 + 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFTLCD panels and SXGA TFT-LCD panels. This driver is applicable to SXGA TFT-LCD panels by input display signal 2 systems (Clock divide). FEATURES • CMOS level input • 384 outputs • Input of 8 bits (gradation data) by 6 dots • Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter • Output dynamic range: VDD2 – 0.2 V to VSS2 + 0.2 V • High-speed data transfer: fCLK = 40 MHz (internal data transfer speed when operating at 3.0 V) • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Display data inversion function (POL21/22) • Logic power supply voltage (VDD1) : 3.3 V ± 0.3 V • Driver power supply voltage (VDD2) : 9.0 V ± 0.5 V • Low power control function (LPC) ORDERING INFORMATION Part Number Package TCP (TAB package) µ PD16750N-xxx Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13719EJ4V0DS00 (4th edition) Date Published April 2000 NS CP (K) Printed in Japan The mark • shows major revised points. © 1998 µPD16750 1. BLOCK DIAGRAM STHR R,/L CLK STB C1 C2 STHL VDD1 VSS1 C63 C64 64-bit bidirectional shift register D00 - D07 D10 - D17 D20 - D27 D30 - D37 D40 - D47 D50 - D57 POL21 POL22 Data register POL Latch VDD2 Level shifter VSS2 V0 - V15 D/A converter Voltage follower output LPC S1 S2 S3 S384 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 S2 S383 S384 V7 V8 V15 ····· V0 Multiplexer 8 8-bit D/A converter 8 ····· POL 2 Data Sheet S13719EJ4V0DS00 µPD16750 3. PIN CONFIGURATION (µPD16750N-xxx) • • VSS2 VDD2 V14 V12 V10 V8 V6 V4 V2 V0 R,/L D50 D51 D52 D53 D54 D55 D56 D57 D40 D41 D42 D43 D44 D45 D46 D47 D30 D31 D32 D33 D34 D35 D36 D37 POL21 POL22 POL STB STHL VDD1 CLK VSS1 LPC STHR D20 D21 D22 D23 D24 D25 D26 D27 D10 D11 D12 D13 D14 D15 D16 D17 D00 D01 D02 D03 D04 D05 D06 D07 V1 V3 V5 V7 V9 V11 V13 V15 VDD2 VSS2 S384 S383 S382 Copper Foil Surface S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S13719EJ4V0DS00 3 µPD16750 4. PIN FUNCTIONS Pin Symbol S1 to S384 D00 to D07 D10 to D17 D20 to D27 D30 to D37 D40 to D47 D50 to D57 R,/L Shift direction control These refer to the start pulse input/output pins when driver ICs are connected in cascade. input The shift directions of the shift registers are as follows. R,/L = H R,/L = L STHR Right shift start pulse R,/L = H input/output STHL Left shift start pulse input/output CLK Shift clock input R,/L = L R,/L = H R,/L = L : STHR input, S1 → S384, STHL output : STHL input, S384 → S1, STHR output : Becomes the start pulse input pin. : Becomes the start pulse output pin. : Becomes the start pulse output pin. : Becomes the start pulse input pin. Pin Name Driver output Display data input Description The D/A converted 256-gray-scale analog voltage is output. The display data is input with a width of 48 bits, viz., the gray scale data (8 bits) by 6 dots (2 pixels). DX0: LSB, DX7: MSB Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge of the 64th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. STB Latch input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input POL = L : The S2n–1 ou.


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