Document
INTEGRATED CIRCUITS
DATA SHEET
PCF84C12A 8-bit microcontroller
Product specification Supersedes data of 1996 Nov 20 File under Integrated Circuits, IC14 1998 May 11
Philips Semiconductors
Product specification
8-bit microcontroller
CONTENTS 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 13.1 13.2 13.3 14 15 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION (see note 1) BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description INSTRUCTION SET ROM MASK OPTIONS HANDLING LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINES SOLDERING Introduction DIP SO DEFINITIONS LIFE SUPPORT APPLICATIONS
PCF84C12A
1998 May 11
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Philips Semiconductors
Product specification
8-bit microcontroller
1 FEATURES 2 GENERAL DESCRIPTION
PCF84C12A
• Manufactured in silicon gate CMOS process • 8-bit CPU, ROM, RAM, I/O in a 20-lead package • 1 kbyte ROM • 64 byte RAM • Over 100 instructions (based on MAB8048) all of 1 or 2 cycles • 13 quasi-bidirectional I/O port lines • 8-bit programmable timer/event counter 1 • Two single-level vectored interrupts: – external – 8-bit programmable timer/event counter 1 • Two test inputs, one of which also serves as the external interrupt input • Stop and Idle modes • Supply voltage: 2.5 to 5.5 V • Clock frequency: 1 to 16 MHz • Operating temperature: −40 to +85 °C. 3 ORDERING INFORMATION TYPE NUMBER(1) NAME PCF84C12AP PCF84C12AT Note DIP20 SO20
This data sheet details the specific properties of the PCF84C12A. The shared properties of the PCF84CxxxA family of microcontrollers are described in the “PCF84CxxxA family” data sheet, which should be read in conjunction with this publication. Note that the devices described in this data sheet do not feature I2C-bus compatibility or derivative logic, so the information given in the family data sheet about these features can be ignored. The PCF84C12A is a general purpose CMOS microcontroller with 1 kbyte of program memory. It includes 64 bytes of RAM and 13 I/O port lines. The instruction set is based on the MAB8048 and is a sub-set of that listed in the “PCF84CxxxA family” data sheet.
PACKAGE DESCRIPTION plastic dual in-line package; 20 leads (300 mil) plastic small outline package; 20 leads; body width 7.5 mm VERSION SOT146-1 SOT163-1
1. Please refer to the Order Entry Form (OEF) for these devices for the full type number to use when ordering. This type number will also specify the required program and ROM mask options.
1998 May 11
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INTERNAL CLOCK FREQ. 30 32 TIMER/ EVENT COUNTER TEST 1 5 8
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Philips Semiconductors
8-bit microcontroller
BLOCK DIAGRAM
P1.0 to P1.4 3 PORT 1 BUFFER PORT 1 FLIP-FLOPS RESIDENT ROM 1 kbyte (PCF84C12A) 2 kbytes (PCF84C22A) 4 kbytes (PCF84C42A) DECODE
P0.7 to P0.0
PORT 0 BUFFER PORT 0 FLIP-FLOPS
MEMORY BANK FLIP-FLOPS
HIGHER PROGRAM COUNTER
LOWER PROGRAM COUNTER
PROGRAM STATUS WORD
5
8
8
8
8
8
8
8
8
8 MULTIPLEXER REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 8 LEVEL STACK (VARIABLE LENGTH) OPTIONAL SECOND REGISTER BANK
INT / T0 INTERRUPT
RESET INITIALIZE
XTAL 1
XTAL 2
handbook, full pagewidth
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INTERRUPT LOGIC ACCUMULATOR TEMPORARY REGISTER 1 TEMPORARY REGISTER 2 RAM ADDRESS REGISTER timer interrupt ARITHMETIC LOGIC UNIT INSTRUCTION REGISTER & DECODER INT / T0 (8) external interrupt DECIMAL ADJUST STOP IDLE CONDITIONAL BRANCH LOGIC TEST 1 TIMER FLAG CARRY ACC ACC BIT TEST RESIDENT RAM ARRAY 64 bytes
MBC951
D E C O D E
DATA STORE
PCF84C12A
Product specification
CONTROL & TIMING
OSCILLATOR
Fig.1 Block diagram of PCF84C12A.
Philips Semiconductors
Product specification
8-bit microcontroller
5 5.1 PINNING INFORMATION Pinning 5.2 Pin description
PCF84C12A
Table 1
DIP20 and SO20 packages PIN 1 to 8 TYPE I/O DESCRIPTION Port 0: 8-bit quasi-bidirectional I/O port Interrupt/Test 0 ground Test 1/count input of 8-bit timer/event counter 1 crystal oscillator input or external clock input crystal oscillator output reset input Port 1: 4-bit quasi-bidirectional I/O port positive supply
SYMBOL
handbook, halfpage
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 INT/T0
1 2 3 4 5
20 V DD 19 18 17 16 P1.4 P1.3 P1.2 P1.1 P1.0 RESET XTAL2 XTAL1 T1
P0.0 to P0.7
INT/T0 VSS T1
9 10 11
I P I
PCF84C12A
6 7 8 9 15 14 13 12 11
MBK778
XTAL1
12
I
XTAL2 RESET P1.0 to P1.4
13 14 15 to 19
O I I/O
VSS 10
Fig.2 Pin configuration. VDD 6 INSTRUCTION SET 20 P
Since the I2C-bus interface, Port 2 and derivative logic are not provided, instructions associated with these functions are not available. ROM space is restr.