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4-bank/ LVTTL. UPD45128163 Datasheet

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4-bank/ LVTTL. UPD45128163 Datasheet






UPD45128163 LVTTL. Datasheet pdf. Equivalent




UPD45128163 LVTTL. Datasheet pdf. Equivalent





Part

UPD45128163

Description

128M-bit Synchronous DRAM 4-bank/ LVTTL

Manufacture

NEC

Datasheet
Download UPD45128163 Datasheet


NEC UPD45128163

UPD45128163; DATA SHEET MOS INTEGRATED CIRCUIT µPD 45128441, 45128841, 45128163 128M-bit S ynchronous DRAM 4-bank, LVTTL Descript ion The µPD45128441, 45128841, 4512816 3 are high-speed 134,217,728-bit synchr onous dynamic random-access memories, o rganized as 8,388,608 × 4 × 4, 4,194, 304 × 8 × 4, 2,097,152 × 16 × 4 (wo rd × bit × bank), respectively. The s ynchronous DRAMs achieved hi.


NEC UPD45128163

gh-speed data transfer using the pipelin e architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs ar e compatible with Low Voltage TTL (LVTT L). These products are packaged in 54-p in TSOP (II). Features • Fully Synch ronous Dynamic RAM, with all signals re ferenced to a positive clock edge • P ulsed interface • Poss.


NEC UPD45128163

ible to assert random column address in every cycle • Quad internal banks con trolled by BA0(A13) and BA1(A12) • By te control (×16) by LDQM and UDQM • Programmable Wrap sequence (Sequential / Interleave) • Programmable burst le ngth (1, 2, 4, 8 and full page) • Pro grammable /CAS latency (2 and 3) • Au tomatic precharge and controlled precha rge • CBR (Auto) refresh and se.



Part

UPD45128163

Description

128M-bit Synchronous DRAM 4-bank/ LVTTL

Manufacture

NEC

Datasheet
Download UPD45128163 Datasheet




 UPD45128163
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0(A13) and BA1(A12)
Byte control (×16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
• ×4, ×8, ×16 organization
Single 3.3 V ± 0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M12650EJBV0DS00 (11th edition)
Date Published April 2000 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
1997





 UPD45128163
Ordering Information
Part number
µPD45128441G5-A75-9JF
µPD45128441G5-A80-9JF
µPD45128441G5-A10-9JF
µPD45128441G5-A10B-9JF
µPD45128841G5-A75-9JF
µPD45128841G5-A80-9JF
µPD45128841G5-A10-9JF
µPD45128841G5-A10B-9JF
µPD45128163G5-A75-9JF
µPD45128163G5-A80-9JF
µPD45128163G5-A10-9JF
µPD45128163G5-A10B-9JF
µPD45128441, 45128841, 45128163
Organization
(word × bit × bank)
8M × 4 × 4
4M × 8 × 4
2M × 16 × 4
Clock frequency
MHz (MAX.)
133
125
100
100
133
125
100
100
133
125
100
100
Package
54-pin Plastic TSOP (II)
(10.16mm (400))
2 Data Sheet M12650EJBV0DS00





 UPD45128163
µPD45128441, 45128841, 45128163
Part Number
[ x4, x8 ]
µPD45128841G5 - A75
NEC Memory
Synchronous DRAM
Memory density
128 : 128M bits
Organization
4 : x4
8 : x8
Minimum cycle time
75 : 7.5 ns (133 MHz)
80 : 8 ns (125 MHz)
10 : 10 ns (100 MHz)
10B: 10 ns (100 MHz)
Number of banks
4 : 4 banks
Interface
1 : LVTTL
[ x16 ]
163
Low voltage
A : 3.3 V ± 0.3 V
Package
G5 : TSOP (II)
Organization
16 : x16
Number of banks
and Interface
3 : 4 banks, LVTTL
Data Sheet M12650EJBV0DS00
3



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