W158 Datasheet: Spread Spectrum System Frequency Synthesizer





W158 Spread Spectrum System Frequency Synthesizer Datasheet

Part Number W158
Description Spread Spectrum System Frequency Synthesizer
Manufacture Cypress Semiconductor
Total Page 12 Pages
PDF Download Download W158 Datasheet PDF

Features: W158 Spread Spectrum System Frequency S ynthesizer Features • Maximized EMI s uppression using Cypress’s spread spe ctrum technology • Intel® CK98 Speci fication compliant • 0.5% downspread outputs deliver up to 10 dB lower EMI Four skew-controlled copies of CPU o utput • Eight copies of PCI output (s ynchronous w/CPU output) • Four copie s of 66-MHz fixed frequency 3.3V clock • Two copies of CPU/2 outputs for syn chronous memory reference • Three cop ies of 16.67-MHz IOAPIC clock, synchron ous to CPU clock • One copy of 48-MHz USB output • Two copies of 14.31818- MHz reference clock • Programmable to 133- or 100-MHz operation • Power ma nagement control pins for clock stop an d shut down • Available in 56-pin SSO P CPU Output Jitter: .................. .................................... 15 0 ps CPUdiv2, IOAPIC Output Jitter: ... ...............................250 ps 4 8 MHz, 3V66, PCI Output Jitter: ....... ......................... 500 ps CPU0:3, CPUdiv2_ 0:1 Output Skew: ..........................

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W158
Spread Spectrum System Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Intel® CK98 Specification compliant
• 0.5% downspread outputs deliver up to 10 dB lower EMI
• Four skew-controlled copies of CPU output
• Eight copies of PCI output (synchronous w/CPU output)
• Four copies of 66-MHz fixed frequency 3.3V clock
• Two copies of CPU/2 outputs for synchronous memory
reference
• Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and shut
down
• Available in 56-pin SSOP
Key Specifications
Supply Voltages: ...................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
X1
X2
CPU_STOP#
SPREAD#
SEL0
SEL1
SEL133/100#
XTAL
OSC
PLL 1
2
REF0:1
STOP
Clock
Logic
÷2
÷2/÷1.5
STOP
Clock
Logic
4
CPU0:3
2
CPUdiv2_0:1
4
3V66_0:3
PWRDWN#
PCI_STOP#
÷2
Power
Down
Logic
STOP
Clock
Logic
÷2
1
PCI_F
7
PCI1:7
3
IOAPIC0:2
CPU Output Jitter: ...................................................... 150 ps
CPUdiv2, IOAPIC Output Jitter: ..................................250 ps
48 MHz, 3V66, PCI Output Jitter: ................................ 500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
3V66_0:3, IOAPIC0:2 Output Skew: ...........................250 ps
CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads)
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset: ............ 1.5 to 4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-kpull-up
resistors
Table 1. Pin Selectable Frequency[1]
SEL133/100#
CPU0:3 (MHz)
PCI
1
133 MHz
33.3 MHz
0
100 MHz
33.3 MHz
Note:
1. See Table 2 for complete mode selection details.
Pin Configuration
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDQ2
55 IOAPIC2
54 IOAPIC1
53 IOAPIC0
52 GND
51 VDDQ2
50 CPUdiv2_1
49 CPUdiv2_0
48 GND
47 VDDQ2
46 CPU3
45 CPU2
44 GND
43 VDDQ2
42 CPU1
41 CPU0
40 GND
39 VDDQ3
38 GND
37 PCI_STOP#
36 CPU_STOP#
35 PWRDWN#
34 SPREAD#
33 SEL1
32 SEL0
31 VDDQ3
30 48MHz
29 GND
Three-state
Logic
PLL2
Intel is a registered trademark of Intel Corporation.
1
48MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 12, 1999, rev. **

                    
              






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