W182-5 Datasheet PDF | Cypress Semiconductor





W182-5 Datasheet PDF Download

Part Number W182-5
Description Full Feature Peak Reducing EMI Solution
Manufacture Cypress Semiconductor
Total Page 8 Pages
PDF Download Download W182-5 Datasheet PDF

Features: W182 Full Feature Peak Reducing EMI Sol ution Features • Cypress PREMIS™ fa mily offering • Generates an EMI opti mized clocking signal at the output • Selectable output frequency range • Single 1.25% or 3.75% down or center sp read output • Integrated loop filter components • Operates with a 3.3 or 5 V supply • Low power CMOS design • Available in 14-pin SOIC (Small Outline Integrated Circuit) Table 1. Modulatio n Width Selection SS% 0 1 W182 Output F in ≥ Fout ≥ Fin – 1.25% Fin ≥ F out ≥ Fin – 3.75% W182-5 Output Fin + 0.625% ≥ Fin≥ – 0.625% Fin + 1 .875% ≥ Fin≥ –1.875% Table 2. Fr equency Range Selection FS2 0 0 1 1 FS1 0 1 0 1 Frequency Range 8 MHz ≤ FIN ≤ 10 MHz 10 MHz ≤ FIN ≤ 15 MHz 15 MHz ≤ FIN ≤ 18 MHz 18 MHz ≤ FIN ≤ 28 MHz Key Specifications Supply V oltages: .............................. ............. VDD = 3.3V±5% or VDD = 5 V±10% Frequency Range: ............... ............... 8 MHz ≤ Fin ≤ 28 MHz Cycle to Cycle Jitter: ........................................ 300 ps (max.) Selectab.

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W182-5 datasheet
W182
Full Feature Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz Fin 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
SS%
0
1
W182
Output
Fin Fout Fin
– 1.25%
Fin Fout Fin
– 3.75%
W182-5
Output
Fin + 0.625% Fin
– 0.625%
Fin + 1.875% Fin
–1.875%
Table 2. Frequency Range Selection
FS2 FS1
00
01
10
11
Frequency Range
8 MHz FIN 10 MHz
10 MHz FIN 15 MHz
15 MHz FIN 18 MHz
18 MHz FIN 28 MHz
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
XTAL
Input
X1
X2
W182
Spread Spectrum
Output
(EMI suppressed)
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
1
2
3
4
5
6
7
14 REFOUT
13 OE#
12 SSON#
11 Reset
10 VDD
9 VDD
8 CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
W182
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 8, 2000, rev. *A

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