W24100 Datasheet: 128K x 8 CMOS STATIC RAM





W24100 128K x 8 CMOS STATIC RAM Datasheet

Part Number W24100
Description 128K x 8 CMOS STATIC RAM
Manufacture Winbond
Total Page 11 Pages
PDF Download Download W24100 Datasheet PDF

Features: Preliminary W24100 GENERAL DESCRIPTION 128K × 8 CMOS STATIC RAM The W24100 is a normal-speed, very low-power CMOS static RAM organized as 131072 × 8 bit s that operates on a single 5-volt powe r supply. This device is manufactured u sing Winbond's high performance CMOS te chnology. FEATURES • Low power consu mption: − Active: 385 mW (max.) • A ccess time: 70 nS • Single 5V power s upply • Fully static operation • Al l inputs and outputs directly TTL compa tible • Three-state outputs • Batt ery back-up operation capability • Da ta retention voltage: 2V (min.) • Pac kaged in 32-pin 600 mil DIP, 450 mil SO P, standard type one TSOP (8 mm × 20 m m) and small type one TSOP (8 mm × 13. 4 mm) PIN CONFIGURATIONS BLOCK DIAGRA M NC 1 A16 2 32 VDD 31 A15 A14 3 30 CS2 A12 4 A7 5 29 WE 28 A13 A6 6 2 7 A8 A5 7 26 A9 32-pin A4 8 SOP 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CS1 A0 12 21 I/O 8 I/O1 13 20 I/O 7 I/O2 14 19 I/O 6 I/O3 15 VSS 16 18 I/O5 17 I/O4 A11 .

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Preliminary W24100
GENERAL DESCRIPTION
128K × 8 CMOS STATIC RAM
The W24100 is a normal-speed, very low-power CMOS static RAM organized as 131072 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
Low power consumption:
Active: 385 mW (max.)
Access time: 70 nS
Single 5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 32-pin 600 mil DIP, 450 mil SOP,
standard type one TSOP (8 mm × 20 mm) and
small type one TSOP (8 mm × 13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
NC 1
A16 2
32 VDD
31 A15
A14 3
30 CS2
A12 4
A7 5
29 WE
28 A13
A6 6
27 A8
A5 7
26 A9
32-pin
A4 8
SOP 25 A11
A3 9
24 OE
A2 10
23 A10
A1 11
22 CS1
A0 12
21 I/O 8
I/O1 13
20 I/O 7
I/O2 14
19 I/O 6
I/O3 15
VSS 16
18 I/O5
17 I/O4
A11
A9
A8
A13
WE
CS2
A15
VDD
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
TSOP
32 OE
31 A10
30 CS1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 VSS
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3
CLK GEN.
PRECHARGE CKT.
A16
A14
A12 R
A4 O CORE CELL ARRAY
W
A3 1024 ROWS
D
A2 E 128 X 8 COLUMNS
C
A7 O
D
A6 E
R
A5
A9
I/O1
:
I/O8
DATA
CNTRL.
I/O CKT.
COLUMN DECODER
CLK
GEN.
WE
CS1
CS2
OE
A15 A13 A8 A1 A0 A11A10
PIN DESCRIPTION
SYMBOL
A0A16
I/O1I/O8
CS1, CS2
WE
OE
VDD
VSS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
Publication Release Date: October 1999
- 1 - Revision A1

                    
           






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