W25P022A Datasheet: 64K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM





W25P022A 64K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM Datasheet

Part Number W25P022A
Description 64K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
Manufacture Winbond
Total Page 17 Pages
PDF Download Download W25P022A Datasheet PDF

Features: W25P022A 64K × 32 BURST PIPELINED HIGH -SPEED CMOS STATIC RAM GENERAL DESCRIPT ION The W25P022A is a high-speed, low- power, synchronous-burst pipelined CMOS static RAM organized as 65,536 × 32 b its that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium burst mode and linear burst mode. The mode to be executed is controlled by t he LBO pin. Pipelining or non-pipelinin g of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation. The W25P022A supports bo th 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The default mod e is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of pin 42 should not be changed after power up. The 2T/2T mode will sus tain one cycle of valid data output in a burst read cycle when the device is d eselected by CE2/ CE3 . This mode suppo rts 3-1-1-11-1-1-1 in a two-bank, back- to-back burst read cycle. On the other hand, the 2T/1T mode dis.

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W25P022A
64K × 32 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
GENERAL DESCRIPTION
The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM
organized as 65,536 × 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports both Pentiumburst mode and linear burst mode. The mode to be
executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by
the FT pin. A snooze mode reduces power dissipation.
The W25P022A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The
default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of
pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data
output in a burst read cycle when the device is deselected by CE2/ CE3 . This mode supports 3-1-1-1-
1-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables
data output within one cycle in a burst read cycle when the device is deselected by CE2/ CE3 . In this
mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
Synchronous operation
High-speed access time: 6/7 nS (max.)
Single +3.3V power supply
Individual byte write capability
3.3V LVTTL compatible I/O
Clock-controlled and registered input
Asynchronous output enable
BLOCK DIAGRAM
Pipelined/non-pipelined data output capability
Supports snooze mode (low-power state)
Internal burst counter supports Intel burst mode
& linear burst mode
Supports both 2T/2T & 2T/1T mode
Packaged in 100-pin QFP or TQFP
A(15:0)
CLK
CE(3:1)
GW
BWE
BW(4:1)
OE
ADSC
ADSP
ADV
LBO
FT
ZZ
MS
INPUT
REGISTER
CONTROL
LOGIC
REGISTE
R
64K X 32
CORE
ARRAY
DATA I/O
REGISTER
I/O(32:1)
Publication Release Date: September 1996
- 1 - Revision A1

                    
                    






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