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W83301DR-O Dataheets PDF



Part Number W83301DR-O
Manufacturers Winbond
Logo Winbond
Description ACPI-STR Controller
Datasheet W83301DR-O DatasheetW83301DR-O Datasheet (PDF)

Winbond ACPI-STR Controller W83301DR-O Date: 2002/07 Revision: 1.0 W83301DR-O Data Sheet Revision History Pages 1 N.A. Dates 07/2002 Version 1.0 Version on Web 1.0 1st Release Main Contents Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems w.

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Winbond ACPI-STR Controller W83301DR-O Date: 2002/07 Revision: 1.0 W83301DR-O Data Sheet Revision History Pages 1 N.A. Dates 07/2002 Version 1.0 Version on Web 1.0 1st Release Main Contents Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83301DR-O 1. General Description The W83301DR-O is an ACPI-compliant controller for microprocessor and other computer applications. The part provides functions - two switch controllers to generate a 5VDL and a 3.3 VDL voltage from ATX power supply; a linear controller – STR1 (2.5VDUAL), and a bus termination controller – STR2 (1.25 VDUAL) for high-speed bus such as RDRAM/DDRAM current sinking and sourcing. Besides, the W83301DR-O also can provide extra voltage up to 0.4V in each regulator output for over-clocking application and more performance by two hardware pins - VSET2, and VSET3. In order to reduce the customer’s cost, and simplify the circuit design, the W83301DR-O integrates a chargepump engine into the chip to provide higher driving voltage to drive single N-channel MOSFETs. The W83301DR-O also offers PWOK and over current detection to protect each output and soft-start protects all linear controllers from rush current attack. The W83301DR-O is available in a 24-pin TSSOP package. 2. Features Provides various voltages for DDR-STR applications Provide a switch controller to generate 5VDUAL voltage Provide a switch controller to generate 3.3VDUAL voltage Linear controller STR1–2.5VDUAL for DDR application Bus termination controller STR2 –1.25VDUAL for high speed bus termination to sink and drive redundant current Provide a switch 5VDLEN pin to enable/disable 5VDL output in S5 state for USB application Supports DDR ACPI-STR Functions Drives all N-Channel MOSFETs Power-Up Softstart for all controllers Up to 0.4V/0.2V incremental voltage on STR1/STR2 for over-clocking application. Under-Voltage Fault Monitor Soft-Start function 24-Pin TSSOP Package 1 Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 3. W83301DR-O Pin Configuration Reserved BTDRV BTSEN BTSINK Reserved Vss 5VSB C1 C2 1 2 3 4 5 6 7 8 9 24 Reserved 23 STR1DRV 22 STR1SEN 21 SS inbond W83301DR-O 20 PWOK 19 3VDRV/5VDRV 18 5VDLSB 17 3VDLSB 16 3VSBSEN 15 S3# 14 S5# 13 VSET2 ChrPmp 10 5VDLEN# 11 VSET3 12 2 Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 4. Pin Description SYMBOL PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FUNCTION Reserved BTDRV BTSEN BTSINK Reserved Vss 5VSB C1 C2 ChrPmp 5VDLEN# VSET3 VSET2 S5# S3# 3VSBSEN 3VDLSB 5VDLSB 3VDRV/5VDRV PWOK SS STR1SEN STR1DRV Reserved 21 22 23 24 Pin Reserved BT Current Source. Connect this pin to the gate of a suitable N-channel MOSFET for driving bus termination regulator output. BT Sense. Connect this pin to the bus termination regulator output. BT Current Sink. This pin is used to drive a N-channel MOSFET to sink the redundant current in the high-speed bus. Function Reserved. Pull up this pin to +5VSB through a 1.5 Kohm resistor. Power Ground. Connect this pin to ground. Power 5VSB. Input 5VSB supply. Charge Pump Cap. Attach flying capacitor between this pin and C2 to generate internally used high voltage from 5V power supply. Charge Pump Cap. Attach flying capacitor between this pin and C1 to generate internally used high voltage from 5V power supply. Charge Pump output. This pin produces voltage doubled 5V supply by charge pumping. Bypass with a 0.1uF capacitor. 5VDL Enable. Control 5VDL voltage output. Pull-up internally. Voltage Selection. Combine with VSET2 to select output voltages of STR regulators. Voltage Selection. Combine with VSET3 to select output voltages of STR regulators. S5 Signal. Control signal governing the soft off state S5. Pull-up internally. S3 Signal. Control signal governing the soft off state S3. Pull-up internally. 3VDL Sense. Connect this pin to the STR1 output. 3VDL Drive. Connect this pin to the gate of a suitable N-channel MOSFET for driving STR1 output. 5VSB Output Control. Connect this pin to the gate of a N-MOSFET to output 5VSB power to 5VDL. 3.3V/5V Output Control. Connect this pin to the gate of a N-MOSFET to output 3.3V/5V power to 3.3VDL/5VDL. Power OK. Open collector input/output. Used to indicate the ready of 5Vin supply. If any STR supply occurs over current and induce under-voltage, PWOK will be pull down. Soft-Start. Attach a capacitor (0.033u) to this pin to determine the softstart rate. A ramp generated by charging t.


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