Document
WT8048
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DESCRIPTION
DPMS (Display Power Management Signaling) Detector for Green Monitor Aug. 31, 1995
The WT8048 is a 8 pin P-DIP package IC, designed for the application of Power Saving Monitor or Green Monitor.
As per DPMS proposal, the WT8048 provides a detective circuit of monitor power management for the convenience of designers in designing Power Saving Monitor.
FEATURES
{ Accepting two seperated H&V synchronous signals with positive/ negative polarity. { Capable of processing horizontal frequency between 0Hz to 100kHz, and vertical frequency between 0Hz to 100Hz.
{ Power Saving mode - It can detect the conditions of monitor to decide which will be selected as following: ON mode / STAND_BY mode / SUSPEND mode / OFF mode.
{ An Override mode is defined to override the DPMS function during the design, test, burn-in manufacture or diagnostic process if desired.
APPLICATION
{ DPMS mode's detection for Green Monitor
Weltrend Semiconductor, Inc.
2F., No. 24, Ind. E. 9th Rd., Science-Based Ind. Park, Hsin-Chu, Taiwan, R. O. C. Tel: 886-35-780241 Fax: 886-35-7704191
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ORDERING INFORMATION
Part No. WT8048 WT8048N1 WT8048N2 *WT8048N3 *WT8048N4 Package P-DIP 8L P-DIP 8L P-DIP 8L P-DIP 8L P-DIP 8L
WT8048
Description OSC with 32768Hz Crystal 1. OSC with external resistor 2. With mute function 1. OSC with external resistor 2. Without mute function 1. OSC with 3.58MHz resonator 2. With mute function 1. OSC with 3.58MHz resonator 2. Without mute function
Note: "*" means "not available".
PIN CONFIGURATION
WT8048N1 / N3
HIN 1 8 VDD HIN
WT8048 / N2 / N4
1 8 VDD
VIN
2
7
OFF STD_BY + SUSPEND MUTE
VIN
2
7
OFF
OSC
3
6
OSC
3
6
SUSPEND
VSS
4
5
VSS
4
5
STD_BY
2
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ABSOLUTE MAXIMUM RATING
ITEM Digital Supply Voltage Horizontal Sync. Input Voltage Vertical Sync. Input Voltage Power dissipation Operating Temperature Range Storage Temperature Range SYMBOL VDD VHS VVS PD TOPT TSTG VALUE 5.5 VDD(5)+0.3 VDD(5)+0.3 30 0¡ ã 70 -40¡ ã 125
WT8048
UNIT V VPP VPP mW ¢ J ¢ J
RECOMMENDED OPERATING CONDITIONS
ITEM Digital Supply Voltage Supply Current (Stand-by) Synchronous Input Voltage Low Synchronous Input Voltage High SYMBOL VDD(5) IP VIL VIH MIN. 4.5 TYP. 5 MAX. 5.5 1 0.8 5.5 UNIT V mA VPP VPP
2.4
4
3
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ELECTRICAL CHARACTERISTICS
A. WT8048
(VDD=5V, TOPT=24¢ J , FOSC=32768Hz)
WT8048
ITEM Input Current (HIN, VIN), when VIN=5V Open Drain Output Low, when IOL = 6mA Open Drain Sink Current, when VOL = 0.4V Input Current (OSC), when VIN = 5V
SYMBOL MIN. IIN1 VOL VOL IIN3
TYP.
MAX. UNIT 5 £ g A 0.4 VPP 6 mA 5 £ g A
B. WT8048N1 / N2
(VDD=5V, TOPT=24¢ J , FOSC= 450KHz)
ITEM Input Current (HIN, VIN), when VIN=5V Open Drain Output Low, when IOL = 6mA Open Drain Sink Current, when VOL = 0.4V Input Current (OSC), when VIN = 5V
SYMBOL MIN. IIN1 VOL VOL IIN3
TYP.
MAX. UNIT 5 £ g A 0.4 VPP 6 mA 15 mA
C. WT8048N3 / N4
(VDD=5V, TOPT=24¢ J , FOSC= 3.58MHz)
ITEM Input Current (HIN, VIN), when VIN=5V Open Drain Output Low, when IOL = 6mA Open Drain Sink Current, when VOL = 0.4V Input Current (OSC), when VIN = 5V
SYMBOL MIN. IIN1 VOL VOL IIN3
TYP.
MAX. UNIT 5 £ g A 0.4 VPP 6 mA 5 £ g A
4
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PIN DESCRIPTION
Pin No.
WT8048N1 /N3 WT8048/ N2/N4
WT8048
Name HSIN VSIN OSC
Function Input terminal of horizontal synchronous signal Input terminal of vertical synchronous signal A clock generator circuit is built into the chip. So, if a resonator is connected to OSC pin and ground, a clock signal can be obtained. Ground Indicate in Stand_By mode Indicate in Mute mode Indicate in Suspend mode Indicate in Suspend and stand_By mode Indicate in Off mode 5 volts power supply
Structure of Terminal
Input, TTL compatible Input, TTL compatible Input
1 2 3
1 2 3
4 5
4 5 6
6
7 8
7 8
VSS STD_BY Mute Suspend Suspend + STD_BY Off VDD
Output, open drain Output, open drain
Output, open drain
5
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APPLICATION DESCRIPTION
DPMS (Display Power Management Signaling) Dection
WT8048
As per DPMS proposal WT8048 provides Monitor Power Management Detection Circuit for the convenience of monitor designers in designing power saving minitors, or the so called "Green Monitors". Please refer to the table 1 as below for power states defined in the DPMS. DPMS requires at least 5 seconds delay before transition from ON state to any power saving state, to avoid unintentionally entering a power saving state during display resoultion changes and timing mode changes. And it can be done instaneously, for the transition between any power saving state.
State On Stand-By Suspend Off
Table 1 Display Power Management Summary Signals DPMS Power Compliance Horizontal Vertical Video Savings Requirement Pulse Pulses Active Mandatory None No Pulses Pulse No Pulses Pulses No Pulses No Pulses Blanked Blanked Blanked Optional Mandatory Mandatory Minimal Substantial Maximum
Recovery Time Not Applicable Short Longer System Dependent
* "No Pulse" represents the frequency of Hsin or Vsin less than or equal .