Document
New Features Repetitive Alarms & Temperature Compensation
4K (512 x 8)
X1228
2-Wire™ RTC
Real Time Clock/Calendar/CPU Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar — Tracks time in Hours, Minutes, and Seconds — Day of the Week, Day, Month, and Year • 2 Polled Alarms (Non-volatile) — Settable on the Second, Minute, Hour, Day of the Week, Day, or Month — Repeat Mode (periodic interrupts) • Oscillator Compensation on chip — Internal feedback resistor and compensation capacitors — 64 position Digitally Controlled Trim Capacitor — 6 digital frequency adjustment settings to ±30ppm • CPU Supervisor Functions — Power On Reset, Low Voltage Sense — Watchdog Timer (SW Selectable: 0.25s, 0.75s, 1.75s, off) • Battery Switch or Super Cap Input • 512 x 8 Bits of EEPROM — 64-Byte Page Write Mode — 8 modes of Block Lock™ Protection — Single Byte Write Capability • High Reliability — Data Retention: 100 years — Endurance: 100,000 cycles per byte • 2-Wire™ Interface interoperable with I2C* — 400kHz data transfer rate • Frequency Output (SW Selectable: Off, 1Hz, 4096Hz, or 32.768kHz) • Low Power CMOS — 1.25µA Operating Current (Typical) • Small Package Options — 14-Lead SOIC and 14-Lead TSSOP
APPLICATIONS • • • • • • • • • • • • • • • Utility Meters HVAC Equipment Audio / Video Components Set Top Box / Television Modems Network Routers, Hubs, Switches, Bridges Cellular Infrastructure Equipment Fixed Broadband Wireless Equipment Pagers / PDA POS Equipment Test Meters / Fixtures Office Automation (Copiers, Fax) Home Appliances Computer Products Other Industrial / Medical / Automotive
BLOCK DIAGRAM
OSC Compensation
X1
32.768kHz
X2
Oscillator
Frequency Divider
1Hz
Timer Calendar Logic
Time Keeping Registers (SRAM)
Battery Switch Circuitry
VCC VBACK
PHZ/IRQ
Select Status Registers (SRAM) Mask
SCL SDA
Serial Interface Decoder
Control Decode Logic
Control/ Registers (EEPROM)
Alarm
Compare Alarm Regs (EEPROM) 4K EEPROM ARRAY
8
RESET
Watchdog Timer Low Voltage Reset
*I2C is a Trademark of Philips.
REV 1.3 3/24/04
www.xicor.com
Characteristics subject to change without notice.
1 of 31
X1228
PIN DESCRIPTIONS
14-Pin TSSOP/SOIC X1 X2 NC NC NC RESET VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC VBACK PHZ/IRQ NC NC SCL SDA
NC = No internal connection
REV 1.3 3/24/04
www.xicor.com
Characteristics subject to change without notice.
2 of 31
X1228
PIN ASSIGNMENTS Pin Number SOIC/TSSOP
1
Symbol
X1
Brief Description
X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1228 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X1 are highly recommended. See Application section for more recommendations. X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1228 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X2 are highly recommended. See Application section for more recommendations. RESET Output – RESET. This is a reset signal output. This signal notifies a host processor that the watchdog time period has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the pullup resistor is 5K Ohms. If unused, tie to ground. VSS. Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz 2-wire interface speeds. Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from the internal oscillator or an interrupt signal output. It is a CMOS output. When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz or inactive. When used as interrupt output, this signal notifies a host processor that an alarm has occurred and an action is required. It is an active LOW output. The control bits for this function are FO1 and FO0 and are found in address 0011h of the Clock Control Memory map. See “Programmable Frequency Ou.