(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a non-volatile write cycle; tWC after a
stop that initiates a non-volatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz, SDA = Open
(6) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz, fSDA = 400KHz, Vcc = 1.22 x Vcc Min
(7) VCC = 0V.
(8) VBACK= 0V.
(9) VSDA=VSCL=VCC, Others=GND or VCC
(10) VSDA=VSCL=VBACK, Others=GND or VBACK
(11) VSDA = GND to VCC, VCLK = GND or VCC
(12) IOL = 3.0mA at 5V, 1.5mA at 2.7V
(13) IOH = -1.0mA at 5V, -0.4mA at 2.7V
(14) Threshold voltages based on the higher of Vcc or Vback.
(15) Driven by external 32.768KHz square wave oscillator on X1, X2 open.
(16) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(17) Periodically sampled and not 100% tested.
CAPACITANCE (TA = 25˚C, f = 1.0 MHz, VCC = 5V)
Output Capacitance (SDA)
Input Capacitance (SCL)
Notes: (1) This parameter is periodically sampled and not 100% tested.
VOUT = 0V
VIN = 0V
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
VCC x 0.1 to VCC x 0.9
VCC x 0.5
Standard Output Load
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR
VCC = 5V (Standard Output Load for testing the device
with VCC = 5.0V)
For VOL= 0.4V
and IOL = 3 mA