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PCK2010 Dataheets PDF



Part Number PCK2010
Manufacturers NXP
Logo NXP
Description CK98 100/133MHz Spread Spectrum System Clock Generator
Datasheet PCK2010 DatasheetPCK2010 Datasheet (PDF)

INTEGRATED CIRCUITS PCK2010 CK98 (100/133MHz) Spread Spectrum System Clock Generator Preliminary specification 1999 Mar 01 Philips Semiconductors Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 FEATURES • Mixed 2.5V and 3.3V operation • Four CPU clocks at 2.5V • Eight PCI clocks at 3.3V, one free-running (synchronous with CPU clocks) PIN CONFIGURATION VSS REF0 REF1 VDD3V XTAL_IN XTAL_OUT VSS PCICLK_F PCICLK1 VDD3V PCICLK2.

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INTEGRATED CIRCUITS PCK2010 CK98 (100/133MHz) Spread Spectrum System Clock Generator Preliminary specification 1999 Mar 01 Philips Semiconductors Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 FEATURES • Mixed 2.5V and 3.3V operation • Four CPU clocks at 2.5V • Eight PCI clocks at 3.3V, one free-running (synchronous with CPU clocks) PIN CONFIGURATION VSS REF0 REF1 VDD3V XTAL_IN XTAL_OUT VSS PCICLK_F PCICLK1 VDD3V PCICLK2 PCICLK3 VSS PCICLK4 PCICLK5 VDD3V PCICLK6 PCICLK7 VSS VSS 3V66_0 3V66_1 VDD3V VSS 3V66_2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD25V APIC2 APIC1 APIC0 VSS VDD25V CPUDIV2_1 CPUDIV2_0 VSS VDD25V CPUCLK3 CPUCLK2 VSS VDD25V CPUCLK1 CPUCLK0 VSS VDD3V VSS PCISTOP CPUSTOP PWRDWN SPREAD SEL1 SEL0 VDD3V 48MHz VSS • Four 3.3V fixed clocks @ 66MHz • Two 2.5V CPUDIV2 clocks @ ½ CPU clock frequency • Three 2.5V IOAPIC clocks @ 16.67 MHz • One 3.3V 48MHz USB clock • Two 3.3V reference clocks @ 14.318 MHz • Reference 14.31818 MHz Xtal oscillator input • 133 MHz or 100 MHz operation • Power management control input pins • LOW CPU clock jitter ≤ 250 ps cycle-cycle • LOW skew outputs • 0.0ns – 1.5ns CPU - 3V66 delay • 1.5ns – 4.0ns 3V66 - PCI delay • 1.5ns – 4.0 ns CPU - IOAPIC delay • Available in 56-pin SSOP package • ±0.5% center spread spectrum capability via select pins; –0.5% down spread spectrum capability via select pins DESCRIPTION The PCK2010 is a clock synthesizer/driver chip for a PentiumII and other similar processors. The PCK2010 has four CPU clock outputs at 2.5V, two CPUDIV2 clock outputs running at ½ CPU clock frequency (66MHz or 50MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz. There are eight PCI clock outputs running at 33MHz. One of the PCI clock outputs is free-running. Additionally, the part has three 2.5V IOAPIC clock outputs at 16.67MHz and two 3.3V reference clock outputs at 14.318MHz. All clock outputs meet Intel’s drive strength, rise/fall time, jitter, accuracy, and skew requirements. The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW. Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW. 3V66_3 VDD3V SEL133/100 SW00352 ORDERING INFORMATION PACKAGES 56-Pin Plastic SSOP TEMPERATURE RANGE 0°C to +70°C OUTSIDE NORTH AMERICA PCK2010 DL NORTH AMERICA PCK2010 DL DRAWING NUMBER SOT371-1 Intel and Pentium are registered trademarks of Intel Corporation. 2 1999 Mar 01 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 PIN DESCRIPTION PIN NUMBER 2,3 5 6 8 9, 11, 12, 14, 15, 17, 18 21, 22, 25, 26 28 30 32, 33 34 35 36 37 41, 42, 45, 46 49, 50 53, 54, 55 4, 10, 16, 23, 27, 31, 39 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 43, 47, 51, 56 SYMBOL REF [0–1] XTAL_IN XTAL_OUT PCICLK_F PCICLK [1–7] 3V66 [0–3] SEL133/100 48MHz SEL [0–1] SPREAD PWRDWN CPUSTOP PCISTOP CPUCLK [0–3] CPUDIV_2 [0–1] IOAPIC [0–2] VDD3V VSS VDD25V FUNCTION 3.3V 14.318 MHz clock output 14.318 MHz crystal input 14.318 MHz crystal output 3.3V free running PCI clock 3.3V PCI clock outputs 3.3V fixed 66MHz clock outputs Select input pin for enabling 133MHz or 100MHz CPU outputs. H = 133MHz, L = 100MHz 3.3V fixed 48MHZ clock output Logic select pins. TTL levels. 3.3V LVTTL input. Enables spread spectrum mode when held LOW. 3.3V LVTTL input. Device enters powerdown mode when held LOW. 3.3V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW. CPUDIV_2 output remains on all the time. 3.3V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW. 2.5V CPU output. 133MHz or 100MHz depending on state of input pin SEL133/100. 2.5V output running at 1/2 CPU clock frequency. 66MHz or 50MHz depending on state of input pin SEL133/100. 2.5V clock outputs running divide synchronous with the CPU clock frequency. Fixed 16.67 MHz limit. 3.3V power supply. Ground 2.5V power supply NOTES: 1. VDD3V, VDD25V and VSS in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the VDD25V pins tied to a 2.5V supply, all remaining VDD pins tied to a common 3.3V supply and all VSS pins being common. 1999 Mar 01 3 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 BLOCK DIAGRAM LOGIC PWRDWN LOGIC XTAL_IN X 14.318 MHZ OSC USBPLL X REF [0–1](14.318 MHz).


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