PCK2510SA

INTEGRATED CIRCUITS PCK2510SA 50–150 MHz 1:10 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group 2000 Dec 01 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA FEATURES Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the PCK2510SA does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the PCK2510SA requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference. The PLL can be bypassed for test purposes by strapping AVCC to ground. The PCK2510SA is characterized for operation from 0 °C to +70 °C. JEDEC compliant operation—PLL remains locked when outputs are disabled. See PCK2510SL for low power version where PLL goes into standby when outputs are disabled. Spread Spectrum clock compatible Operating frequency 50 to 15...